Cortex-M7 handling. 31/3531/2
authorAndreas Bolsch <hyphen0break@gmail.com>
Sun, 26 Jun 2016 11:21:46 +0000 (13:21 +0200)
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>
Wed, 10 Aug 2016 11:02:24 +0000 (12:02 +0100)
- FPU detection and FPU register support added for Cortex-M7.
  There is no apparent difference between FPv4 and FPv5_SP but ...

- Autoincrement range for MEM-AP added for Cortex-M7

This patch together with #3526 replaces #3123 except for stm32f7x.cfg.

Change-Id: I5ed5392e3835674160563ff37d67622a7bf2c877
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/3531
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
src/target/armv7m.h
src/target/cortex_m.c

index bd92d2d..90cad00 100644 (file)
@@ -132,6 +132,8 @@ enum {
 enum {
        FP_NONE = 0,
        FPv4_SP,
+       FPv5_SP,
+       FPv5_DP,
 };
 
 #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
index 012a1a6..a6a9309 100644 (file)
@@ -1875,6 +1875,11 @@ static void cortex_m_dwt_free(struct target *target)
 #define MVFR0_DEFAULT_M4 0x10110021
 #define MVFR1_DEFAULT_M4 0x11000011
 
+#define MVFR0_DEFAULT_M7_SP 0x10110021
+#define MVFR0_DEFAULT_M7_DP 0x10110221
+#define MVFR1_DEFAULT_M7_SP 0x11000011
+#define MVFR1_DEFAULT_M7_DP 0x12000011
+
 int cortex_m_examine(struct target *target)
 {
        int retval;
@@ -1930,21 +1935,33 @@ int cortex_m_examine(struct target *target)
                }
                LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
-               /* test for floating point feature on Cortex-M4 */
                if (i == 4) {
                        target_read_u32(target, MVFR0, &mvfr0);
                        target_read_u32(target, MVFR1, &mvfr1);
 
+                       /* test for floating point feature on Cortex-M4 */
                        if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
                                armv7m->fp_feature = FPv4_SP;
                        }
+               } else if (i == 7) {
+                       target_read_u32(target, MVFR0, &mvfr0);
+                       target_read_u32(target, MVFR1, &mvfr1);
+
+                       /* test for floating point features on Cortex-M7 */
+                       if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
+                               LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
+                               armv7m->fp_feature = FPv5_SP;
+                       } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
+                               LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
+                               armv7m->fp_feature = FPv5_DP;
+                       }
                } else if (i == 0) {
                        /* Cortex-M0 does not support unaligned memory access */
                        armv7m->arm.is_armv6m = true;
                }
 
-               if (armv7m->fp_feature != FPv4_SP &&
+               if (armv7m->fp_feature == FP_NONE &&
                    armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
                        /* free unavailable FPU registers */
                        size_t idx;
@@ -1959,8 +1976,9 @@ int cortex_m_examine(struct target *target)
                        armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
                }
 
-               if ((i == 4 || i == 3) && !armv7m->stlink) {
-                       /* Cortex-M3/M4 has 4096 bytes autoincrement range */
+               if ((i == 3 || i == 4 || i == 7) && !armv7m->stlink) {
+                       /* Cortex-M3/M4/M7 have at least 4096 bytes autoincrement range,
+                        * s. ARM IHI 0031C: MEM-AP 7.2.2 */
                        armv7m->debug_ap->tar_autoincr_block = (1 << 12);
                }