15 files changed:
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 dst_min_alignment, wcount, bytes_remaining = count;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 dst_min_alignment, wcount, bytes_remaining = count;
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
- target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
+ if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
+ {
+ return retval;
+ }
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
int cfi_read_intel_pri_ext(flash_bank_t *bank)
{
int cfi_read_intel_pri_ext(flash_bank_t *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
target_t *target = bank->target;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, command);
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("Could not read bank flash bank information");
return ERROR_FLASH_BANK_INVALID;
}
LOG_ERROR("Could not read bank flash bank information");
return ERROR_FLASH_BANK_INVALID;
}
int cfi_read_spansion_pri_ext(flash_bank_t *bank)
{
int cfi_read_spansion_pri_ext(flash_bank_t *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
target_t *target = bank->target;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("Could not read spansion bank information");
return ERROR_FLASH_BANK_INVALID;
}
LOG_ERROR("Could not read spansion bank information");
return ERROR_FLASH_BANK_INVALID;
}
int cfi_read_atmel_pri_ext(flash_bank_t *bank)
{
int cfi_read_atmel_pri_ext(flash_bank_t *bank)
{
cfi_atmel_pri_ext_t atmel_pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
cfi_atmel_pri_ext_t atmel_pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("Could not read atmel bank information");
return ERROR_FLASH_BANK_INVALID;
}
LOG_ERROR("Could not read atmel bank information");
return ERROR_FLASH_BANK_INVALID;
}
int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xd0, command);
cfi_command(bank, 0xd0, command);
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xff, command);
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
{
}
int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x80, command);
cfi_command(bank, 0x80, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xaa, command);
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x30, command);
cfi_command(bank, 0x30, command);
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xf0, command);
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_command(bank, 0xf0, command);
}
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
-
- return ERROR_OK;
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_erase(struct flash_bank_s *bank, int first, int last)
}
int cfi_erase(struct flash_bank_s *bank, int first, int last)
int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
{
int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (set)
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
if (set)
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
bank->sectors[i].is_protected = 1;
}
else
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
bank->sectors[i].is_protected = 1;
}
else
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
bank->sectors[i].is_protected = 0;
}
bank->sectors[i].is_protected = 0;
}
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
block_status = cfi_get_u8(bank, i, 0x2);
if ((block_status & 0x1) != set)
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
block_status = cfi_get_u8(bank, i, 0x2);
if ((block_status & 0x1) != set)
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_intel_wait_status_busy(bank, 10);
if (retry > 10)
cfi_intel_wait_status_busy(bank, 10);
if (retry > 10)
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x01, command);
cfi_command(bank, 0x01, command);
- target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_intel_wait_status_busy(bank, 100);
}
cfi_intel_wait_status_busy(bank, 100);
}
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
-
- return ERROR_OK;
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
}
int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, address, bank->bus_width, 1, word);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ {
+ return retval;
+ }
/* Commit write operation */
cfi_command(bank, 0xd0, command);
/* Commit write operation */
cfi_command(bank, 0xd0, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
u8 command[8];
cfi_command(bank, 0xaa, command);
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
u8 command[8];
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xa0, command);
cfi_command(bank, 0xa0, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, address, bank->bus_width, 1, word);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
// Unlock
cfi_command(bank, 0xaa, command);
// Unlock
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
// Buffer load command
cfi_command(bank, 0x25, command);
// Buffer load command
cfi_command(bank, 0x25, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ {
+ return retval;
+ }
/* Commit write operation */
cfi_command(bank, 0x29, command);
/* Commit write operation */
cfi_command(bank, 0x29, command);
- target->type->write_memory(target, address, bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
for (i = 0; i < align; ++i, ++copy_p)
{
u8 byte;
for (i = 0; i < align; ++i, ++copy_p)
{
u8 byte;
- target->type->read_memory(target, copy_p, 1, 1, &byte);
+ if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_add_byte(bank, current_word, byte);
}
cfi_add_byte(bank, current_word, byte);
}
for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
{
u8 byte;
for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
{
u8 byte;
- target->type->read_memory(target, copy_p, 1, 1, &byte);
+ if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_add_byte(bank, current_word, byte);
}
cfi_add_byte(bank, current_word, byte);
}
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, current_word);
cfi_command(bank, 0xff, current_word);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ {
+ return retval;
+ }
/* handle unaligned tail bytes */
if (count > 0)
/* handle unaligned tail bytes */
if (count > 0)
for (; i < bank->bus_width; ++i, ++copy_p)
{
u8 byte;
for (; i < bank->bus_width; ++i, ++copy_p)
{
u8 byte;
- target->type->read_memory(target, copy_p, 1, 1, &byte);
+ if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_add_byte(bank, current_word, byte);
}
retval = cfi_write_word(bank, current_word, write_p);
cfi_add_byte(bank, current_word, byte);
}
retval = cfi_write_word(bank, current_word, write_p);
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, current_word);
cfi_command(bank, 0xff, current_word);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
-
- return ERROR_OK;
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
}
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
}
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x90, command);
cfi_command(bank, 0x90, command);
- target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
if (bank->chip_width == 1)
{
if (bank->chip_width == 1)
{
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, command);
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_fixup(bank, cfi_jedec_fixups);
cfi_fixup(bank, cfi_jedec_fixups);
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, command);
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_ERROR("Could not probe bank");
return ERROR_FLASH_BANK_INVALID;
}
LOG_ERROR("Could not probe bank");
return ERROR_FLASH_BANK_INVALID;
}
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0xff, command);
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
}
/* apply fixups depending on the primary command set */
}
/* apply fixups depending on the primary command set */
int cfi_intel_protect_check(struct flash_bank_s *bank)
{
int cfi_intel_protect_check(struct flash_bank_s *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
for (i = 0; i < bank->num_sectors; i++)
{
for (i = 0; i < bank->num_sectors; i++)
{
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
-
- return ERROR_OK;
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_spansion_protect_check(struct flash_bank_s *bank)
{
}
int cfi_spansion_protect_check(struct flash_bank_s *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
int i;
cfi_command(bank, 0xaa, command);
int i;
cfi_command(bank, 0xaa, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x55, command);
cfi_command(bank, 0x55, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
cfi_command(bank, 0x90, command);
cfi_command(bank, 0x90, command);
- target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+ if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ {
+ return retval;
+ }
for (i = 0; i < bank->num_sectors; i++)
{
for (i = 0; i < bank->num_sectors; i++)
{
}
cfi_command(bank, 0xf0, command);
}
cfi_command(bank, 0xf0, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
-
- return ERROR_OK;
+ return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_protect_check(struct flash_bank_s *bank)
}
int cfi_protect_check(struct flash_bank_s *bank)
*/
int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
{
*/
int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
{
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
mem_param_t mem_params[2];
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
mem_param_t mem_params[2];
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
- target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate);
+ if((retval = target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
+ {
+ return retval;
+ }
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
{
/* register flash specific commands */
if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
{
/* register flash specific commands */
- if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
+ if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
LOG_ERROR("couldn't register '%s' commands", args[0]);
{
LOG_ERROR("couldn't register '%s' commands", args[0]);
}
c = malloc(sizeof(nand_device_t));
}
c = malloc(sizeof(nand_device_t));
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
if ((retval = ft2232_read(ft2232_buffer, ft2232_expect_read, &bytes_read)) != ERROR_OK)
{
LOG_ERROR("couldn't read from FT2232");
if ((retval = ft2232_read(ft2232_buffer, ft2232_expect_read, &bytes_read)) != ERROR_OK)
{
LOG_ERROR("couldn't read from FT2232");
int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int i;
int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int i;
/* check whether the interface is already configured */
if (jtag_interface)
/* check whether the interface is already configured */
if (jtag_interface)
{
if (strcmp(args[0], jtag_interfaces[i]->name) == 0)
{
{
if (strcmp(args[0], jtag_interfaces[i]->name) == 0)
{
- if (jtag_interfaces[i]->register_commands(cmd_ctx) != ERROR_OK)
- exit(-1);
+ if ((retval = jtag_interfaces[i]->register_commands(cmd_ctx)) != ERROR_OK)
+ {
+ return retval;
+ }
jtag_interface = jtag_interfaces[i];
jtag_interface = jtag_interfaces[i];
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
{
return retval;
}
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->arm_bkpt)
if (current_instr==arm7_9->arm_bkpt)
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->thumb_bkpt)
if (current_instr==arm7_9->thumb_bkpt)
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int i;
}
/* write DCC code to working area */
}
/* write DCC code to working area */
- target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
+ if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
+ {
+ return retval;
+ }
}
armv4_5_algorithm_t armv4_5_info;
}
armv4_5_algorithm_t armv4_5_info;
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
{
int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm7_9_execute_sys_speed(target);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm7_9_execute_sys_speed(target);
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("failed executing JTAG queue, exiting");
{
LOG_ERROR("failed executing JTAG queue, exiting");
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
{
u8 code[4];
buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
{
u8 code[4];
buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
- target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr);
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code);
+ if((retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
+ {
+ return retval;
+ }
breakpoint->set = 0x11; /* Any nice value but 0 */
}
breakpoint->set = 0x11; /* Any nice value but 0 */
}
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
int embeddedice_get_reg(reg_t *reg)
{
int embeddedice_get_reg(reg_t *reg)
{
- if (embeddedice_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
{
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
{
LOG_ERROR("register read failed");
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
{
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
{
LOG_ERROR("register write failed");
int etb_get_reg(reg_t *reg)
{
int etb_get_reg(reg_t *reg)
{
- if (etb_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
{
LOG_ERROR("BUG: error scheduling etm register read");
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
{
LOG_ERROR("register read failed");
int etb_set_reg(reg_t *reg, u32 value)
{
int etb_set_reg(reg_t *reg, u32 value)
{
- if (etb_write_reg(reg, value) != ERROR_OK)
+ int retval;
+ if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
{
LOG_ERROR("BUG: error scheduling etm register write");
}
buf_set_u32(reg->value, 0, reg->size, value);
}
buf_set_u32(reg->value, 0, reg->size, value);
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
{
LOG_ERROR("register write failed");
int etm_get_reg(reg_t *reg)
{
int etm_get_reg(reg_t *reg)
{
- if (etm_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = etm_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
{
LOG_ERROR("BUG: error scheduling etm register read");
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
{
LOG_ERROR("register read failed");
int etm_set_reg(reg_t *reg, u32 value)
{
int etm_set_reg(reg_t *reg, u32 value)
{
- if (etm_write_reg(reg, value) != ERROR_OK)
+ int retval;
+ if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
{
LOG_ERROR("BUG: error scheduling etm register write");
}
buf_set_u32(reg->value, 0, reg->size, value);
}
buf_set_u32(reg->value, 0, reg->size, value);
int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
{
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
{
LOG_ERROR("register write failed");
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
- target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
+ if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK)
+ {
+ return retval;
+ }
}
/* backup clobbered processor state */
}
/* backup clobbered processor state */
target->type->examine = default_examine;
}
target->type->examine = default_examine;
}
- if (target->type->init_target(cmd_ctx, target) != ERROR_OK)
+ if ((retval = target->type->init_target(cmd_ctx, target)) != ERROR_OK)
{
LOG_ERROR("target '%s' init failed", target->type->name);
{
LOG_ERROR("target '%s' init failed", target->type->name);
}
/* Set up default functions if none are provided by target */
}
/* Set up default functions if none are provided by target */
int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
if (breakpoint->length == 4)
{
/* keep the original instruction in target endianness */
if (breakpoint->length == 4)
{
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
+ if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
/* keep the original instruction in target endianness */
}
else
{
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
+ if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)