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[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28
29 #include "flash.h"
30 #include "target.h"
31 #include "log.h"
32 #include "armv4_5.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
35 #include "types.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39 #include <unistd.h>
40
41 int cfi_register_commands(struct command_context_s *cmd_ctx);
42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int cfi_probe(struct flash_bank_s *bank);
47 int cfi_auto_probe(struct flash_bank_s *bank);
48 int cfi_protect_check(struct flash_bank_s *bank);
49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
55
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
58
59 flash_driver_t cfi_flash =
60 {
61 .name = "cfi",
62 .register_commands = cfi_register_commands,
63 .flash_bank_command = cfi_flash_bank_command,
64 .erase = cfi_erase,
65 .protect = cfi_protect,
66 .write = cfi_write,
67 .probe = cfi_probe,
68 .auto_probe = cfi_auto_probe,
69 .erase_check = default_flash_blank_check,
70 .protect_check = cfi_protect_check,
71 .info = cfi_info
72 };
73
74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
75 {
76 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
77 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
78 };
79
80 /* CFI fixups foward declarations */
81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
84
85 /* fixup after identifying JEDEC manufactuer and ID */
86 cfi_fixup_t cfi_jedec_fixups[] = {
87 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
88 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
94 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
95 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
96 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
97 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_non_cfi, NULL},
98 {CFI_MFR_MX, 0x225b, cfi_fixup_non_cfi, NULL},
99 {CFI_MFR_AMD, 0x225b, cfi_fixup_non_cfi, NULL},
100 {0, 0, NULL, NULL}
101 };
102
103 /* fixup after reading cmdset 0002 primary query table */
104 cfi_fixup_t cfi_0002_fixups[] = {
105 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
106 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
107 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
108 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
109 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
110 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
111 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
112 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
113 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
114 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
115 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
116 {0, 0, NULL, NULL}
117 };
118
119 /* fixup after reading cmdset 0001 primary query table */
120 cfi_fixup_t cfi_0001_fixups[] = {
121 {0, 0, NULL, NULL}
122 };
123
124 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
125 {
126 cfi_flash_bank_t *cfi_info = bank->driver_priv;
127 cfi_fixup_t *f;
128
129 for (f = fixups; f->fixup; f++)
130 {
131 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
132 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
133 {
134 f->fixup(bank, f->param);
135 }
136 }
137 }
138
139 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
140 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
141 {
142 /* while the sector list isn't built, only accesses to sector 0 work */
143 if (sector == 0)
144 return bank->base + offset * bank->bus_width;
145 else
146 {
147 if (!bank->sectors)
148 {
149 LOG_ERROR("BUG: sector list not yet built");
150 exit(-1);
151 }
152 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
153 }
154
155 }
156
157 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
158 {
159 int i;
160
161 /* clear whole buffer, to ensure bits that exceed the bus_width
162 * are set to zero
163 */
164 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
165 cmd_buf[i] = 0;
166
167 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
168 {
169 for (i = bank->bus_width; i > 0; i--)
170 {
171 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
172 }
173 }
174 else
175 {
176 for (i = 1; i <= bank->bus_width; i++)
177 {
178 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
179 }
180 }
181 }
182
183 /* read unsigned 8-bit value from the bank
184 * flash banks are expected to be made of similar chips
185 * the query result should be the same for all
186 */
187 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
188 {
189 target_t *target = bank->target;
190 u8 data[CFI_MAX_BUS_WIDTH];
191
192 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
193
194 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
195 return data[0];
196 else
197 return data[bank->bus_width - 1];
198 }
199
200 /* read unsigned 8-bit value from the bank
201 * in case of a bank made of multiple chips,
202 * the individual values are ORed
203 */
204 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
205 {
206 target_t *target = bank->target;
207 u8 data[CFI_MAX_BUS_WIDTH];
208 int i;
209
210 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
211
212 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
213 {
214 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
215 data[0] |= data[i];
216
217 return data[0];
218 }
219 else
220 {
221 u8 value = 0;
222 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
223 value |= data[bank->bus_width - 1 - i];
224
225 return value;
226 }
227 }
228
229 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
230 {
231 target_t *target = bank->target;
232 u8 data[CFI_MAX_BUS_WIDTH * 2];
233
234 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
235
236 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
237 return data[0] | data[bank->bus_width] << 8;
238 else
239 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
240 }
241
242 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
243 {
244 target_t *target = bank->target;
245 u8 data[CFI_MAX_BUS_WIDTH * 4];
246
247 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
248
249 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
250 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
251 else
252 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
253 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
254 }
255
256 void cfi_intel_clear_status_register(flash_bank_t *bank)
257 {
258 target_t *target = bank->target;
259 u8 command[8];
260
261 if (target->state != TARGET_HALTED)
262 {
263 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
264 exit(-1);
265 }
266
267 cfi_command(bank, 0x50, command);
268 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
269 }
270
271 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
272 {
273 u8 status;
274
275 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
276 {
277 LOG_DEBUG("status: 0x%x", status);
278 alive_sleep(1);
279 }
280
281 /* mask out bit 0 (reserved) */
282 status = status & 0xfe;
283
284 LOG_DEBUG("status: 0x%x", status);
285
286 if ((status & 0x80) != 0x80)
287 {
288 LOG_ERROR("timeout while waiting for WSM to become ready");
289 }
290 else if (status != 0x80)
291 {
292 LOG_ERROR("status register: 0x%x", status);
293 if (status & 0x2)
294 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
295 if (status & 0x4)
296 LOG_ERROR("Program suspended");
297 if (status & 0x8)
298 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
299 if (status & 0x10)
300 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
301 if (status & 0x20)
302 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
303 if (status & 0x40)
304 LOG_ERROR("Block Erase Suspended");
305
306 cfi_intel_clear_status_register(bank);
307 }
308
309 return status;
310 }
311
312 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
313 {
314 u8 status, oldstatus;
315
316 oldstatus = cfi_get_u8(bank, 0, 0x0);
317
318 do {
319 status = cfi_get_u8(bank, 0, 0x0);
320 if ((status ^ oldstatus) & 0x40) {
321 if (status & 0x20) {
322 oldstatus = cfi_get_u8(bank, 0, 0x0);
323 status = cfi_get_u8(bank, 0, 0x0);
324 if ((status ^ oldstatus) & 0x40) {
325 LOG_ERROR("dq5 timeout, status: 0x%x", status);
326 return(ERROR_FLASH_OPERATION_FAILED);
327 } else {
328 LOG_DEBUG("status: 0x%x", status);
329 return(ERROR_OK);
330 }
331 }
332 } else {
333 LOG_DEBUG("status: 0x%x", status);
334 return(ERROR_OK);
335 }
336
337 oldstatus = status;
338 alive_sleep(1);
339 } while (timeout-- > 0);
340
341 LOG_ERROR("timeout, status: 0x%x", status);
342
343 return(ERROR_FLASH_BUSY);
344 }
345
346 int cfi_read_intel_pri_ext(flash_bank_t *bank)
347 {
348 cfi_flash_bank_t *cfi_info = bank->driver_priv;
349 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
350 target_t *target = bank->target;
351 u8 command[8];
352
353 cfi_info->pri_ext = pri_ext;
354
355 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
356 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
357 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
358
359 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
360 {
361 cfi_command(bank, 0xf0, command);
362 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
363 cfi_command(bank, 0xff, command);
364 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
365 LOG_ERROR("Could not read bank flash bank information");
366 return ERROR_FLASH_BANK_INVALID;
367 }
368
369 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
370 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
371
372 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
373
374 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
375 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
376 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
377
378 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
379
380 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
381 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
382
383 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
384 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
385 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
386
387 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
388 if (pri_ext->num_protection_fields != 1)
389 {
390 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
391 }
392
393 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
394 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
395 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
396
397 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
398
399 return ERROR_OK;
400 }
401
402 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
403 {
404 cfi_flash_bank_t *cfi_info = bank->driver_priv;
405 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
406 target_t *target = bank->target;
407 u8 command[8];
408
409 cfi_info->pri_ext = pri_ext;
410
411 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
412 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
413 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
414
415 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
416 {
417 cfi_command(bank, 0xf0, command);
418 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
419 LOG_ERROR("Could not read spansion bank information");
420 return ERROR_FLASH_BANK_INVALID;
421 }
422
423 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
424 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
425
426 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
427
428 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
429 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
430 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
431 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
432 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
433 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
434 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
435 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
436 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
437 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
438 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
439
440 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
441 pri_ext->EraseSuspend, pri_ext->BlkProt);
442
443 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
444 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
445
446 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
447
448
449 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
450 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
451 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
452
453 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
454
455 /* default values for implementation specific workarounds */
456 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
457 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
458 pri_ext->_reversed_geometry = 0;
459
460 return ERROR_OK;
461 }
462
463 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
464 {
465 cfi_atmel_pri_ext_t atmel_pri_ext;
466 cfi_flash_bank_t *cfi_info = bank->driver_priv;
467 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
468 target_t *target = bank->target;
469 u8 command[8];
470
471 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
472 * but a different primary extended query table.
473 * We read the atmel table, and prepare a valid AMD/Spansion query table.
474 */
475
476 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
477
478 cfi_info->pri_ext = pri_ext;
479
480 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
481 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
482 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
483
484 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
485 {
486 cfi_command(bank, 0xf0, command);
487 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
488 LOG_ERROR("Could not read atmel bank information");
489 return ERROR_FLASH_BANK_INVALID;
490 }
491
492 pri_ext->pri[0] = atmel_pri_ext.pri[0];
493 pri_ext->pri[1] = atmel_pri_ext.pri[1];
494 pri_ext->pri[2] = atmel_pri_ext.pri[2];
495
496 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
497 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
498
499 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
500
501 pri_ext->major_version = atmel_pri_ext.major_version;
502 pri_ext->minor_version = atmel_pri_ext.minor_version;
503
504 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
505 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
506 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
507 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
508
509 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
510 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
511
512 if (atmel_pri_ext.features & 0x02)
513 pri_ext->EraseSuspend = 2;
514
515 if (atmel_pri_ext.bottom_boot)
516 pri_ext->TopBottom = 2;
517 else
518 pri_ext->TopBottom = 3;
519
520 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
521 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
522
523 return ERROR_OK;
524 }
525
526 int cfi_read_0002_pri_ext(flash_bank_t *bank)
527 {
528 cfi_flash_bank_t *cfi_info = bank->driver_priv;
529
530 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
531 {
532 return cfi_read_atmel_pri_ext(bank);
533 }
534 else
535 {
536 return cfi_read_spansion_pri_ext(bank);
537 }
538 }
539
540 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
541 {
542 int printed;
543 cfi_flash_bank_t *cfi_info = bank->driver_priv;
544 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
545
546 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
547 buf += printed;
548 buf_size -= printed;
549
550 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
551 pri_ext->pri[1], pri_ext->pri[2],
552 pri_ext->major_version, pri_ext->minor_version);
553 buf += printed;
554 buf_size -= printed;
555
556 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
557 (pri_ext->SiliconRevision) >> 2,
558 (pri_ext->SiliconRevision) & 0x03);
559 buf += printed;
560 buf_size -= printed;
561
562 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
563 pri_ext->EraseSuspend,
564 pri_ext->BlkProt);
565 buf += printed;
566 buf_size -= printed;
567
568 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
569 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
570 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
571
572 return ERROR_OK;
573 }
574
575 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
576 {
577 int printed;
578 cfi_flash_bank_t *cfi_info = bank->driver_priv;
579 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
580
581 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
582 buf += printed;
583 buf_size -= printed;
584
585 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
586 buf += printed;
587 buf_size -= printed;
588
589 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
590 buf += printed;
591 buf_size -= printed;
592
593 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
594 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
595 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
596 buf += printed;
597 buf_size -= printed;
598
599 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
600
601 return ERROR_OK;
602 }
603
604 int cfi_register_commands(struct command_context_s *cmd_ctx)
605 {
606 /*command_t *cfi_cmd = */
607 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
608 /*
609 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
610 "print part id of cfi flash bank <num>");
611 */
612 return ERROR_OK;
613 }
614
615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
616 */
617 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
618 {
619 cfi_flash_bank_t *cfi_info;
620 int i;
621
622 if (argc < 6)
623 {
624 LOG_WARNING("incomplete flash_bank cfi configuration");
625 return ERROR_FLASH_BANK_INVALID;
626 }
627
628 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
629 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
630 {
631 LOG_ERROR("chip and bus width have to specified in bytes");
632 return ERROR_FLASH_BANK_INVALID;
633 }
634
635 cfi_info = malloc(sizeof(cfi_flash_bank_t));
636 cfi_info->probed = 0;
637 bank->driver_priv = cfi_info;
638
639 cfi_info->write_algorithm = NULL;
640
641 cfi_info->x16_as_x8 = 0;
642 cfi_info->jedec_probe = 0;
643 cfi_info->not_cfi = 0;
644
645 for (i = 6; i < argc; i++)
646 {
647 if (strcmp(args[i], "x16_as_x8") == 0)
648 {
649 cfi_info->x16_as_x8 = 1;
650 }
651 else if (strcmp(args[i], "jedec_probe") == 0)
652 {
653 cfi_info->jedec_probe = 1;
654 }
655 }
656
657 cfi_info->write_algorithm = NULL;
658
659 /* bank wasn't probed yet */
660 cfi_info->qry[0] = -1;
661
662 return ERROR_OK;
663 }
664
665 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
666 {
667 cfi_flash_bank_t *cfi_info = bank->driver_priv;
668 target_t *target = bank->target;
669 u8 command[8];
670 int i;
671
672 cfi_intel_clear_status_register(bank);
673
674 for (i = first; i <= last; i++)
675 {
676 cfi_command(bank, 0x20, command);
677 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
678
679 cfi_command(bank, 0xd0, command);
680 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
681
682 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
683 bank->sectors[i].is_erased = 1;
684 else
685 {
686 cfi_command(bank, 0xff, command);
687 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
688
689 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
690 return ERROR_FLASH_OPERATION_FAILED;
691 }
692 }
693
694 cfi_command(bank, 0xff, command);
695 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
696
697 return ERROR_OK;
698 }
699
700 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
701 {
702 cfi_flash_bank_t *cfi_info = bank->driver_priv;
703 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
704 target_t *target = bank->target;
705 u8 command[8];
706 int i;
707
708 for (i = first; i <= last; i++)
709 {
710 cfi_command(bank, 0xaa, command);
711 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
712
713 cfi_command(bank, 0x55, command);
714 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
715
716 cfi_command(bank, 0x80, command);
717 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
718
719 cfi_command(bank, 0xaa, command);
720 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
721
722 cfi_command(bank, 0x55, command);
723 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
724
725 cfi_command(bank, 0x30, command);
726 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
727
728 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
729 bank->sectors[i].is_erased = 1;
730 else
731 {
732 cfi_command(bank, 0xf0, command);
733 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
734
735 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
736 return ERROR_FLASH_OPERATION_FAILED;
737 }
738 }
739
740 cfi_command(bank, 0xf0, command);
741 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
742
743 return ERROR_OK;
744 }
745
746 int cfi_erase(struct flash_bank_s *bank, int first, int last)
747 {
748 cfi_flash_bank_t *cfi_info = bank->driver_priv;
749
750 if (bank->target->state != TARGET_HALTED)
751 {
752 LOG_ERROR("Target not halted");
753 return ERROR_TARGET_NOT_HALTED;
754 }
755
756 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
757 {
758 return ERROR_FLASH_SECTOR_INVALID;
759 }
760
761 if (cfi_info->qry[0] != 'Q')
762 return ERROR_FLASH_BANK_NOT_PROBED;
763
764 switch(cfi_info->pri_id)
765 {
766 case 1:
767 case 3:
768 return cfi_intel_erase(bank, first, last);
769 break;
770 case 2:
771 return cfi_spansion_erase(bank, first, last);
772 break;
773 default:
774 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
775 break;
776 }
777
778 return ERROR_OK;
779 }
780
781 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
782 {
783 cfi_flash_bank_t *cfi_info = bank->driver_priv;
784 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
785 target_t *target = bank->target;
786 u8 command[8];
787 int retry = 0;
788 int i;
789
790 /* if the device supports neither legacy lock/unlock (bit 3) nor
791 * instant individual block locking (bit 5).
792 */
793 if (!(pri_ext->feature_support & 0x28))
794 return ERROR_FLASH_OPERATION_FAILED;
795
796 cfi_intel_clear_status_register(bank);
797
798 for (i = first; i <= last; i++)
799 {
800 cfi_command(bank, 0x60, command);
801 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
802 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
803 if (set)
804 {
805 cfi_command(bank, 0x01, command);
806 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
807 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
808 bank->sectors[i].is_protected = 1;
809 }
810 else
811 {
812 cfi_command(bank, 0xd0, command);
813 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
814 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
815 bank->sectors[i].is_protected = 0;
816 }
817
818 /* instant individual block locking doesn't require reading of the status register */
819 if (!(pri_ext->feature_support & 0x20))
820 {
821 /* Clear lock bits operation may take up to 1.4s */
822 cfi_intel_wait_status_busy(bank, 1400);
823 }
824 else
825 {
826 u8 block_status;
827 /* read block lock bit, to verify status */
828 cfi_command(bank, 0x90, command);
829 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
830 block_status = cfi_get_u8(bank, i, 0x2);
831
832 if ((block_status & 0x1) != set)
833 {
834 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
835 cfi_command(bank, 0x70, command);
836 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
837 cfi_intel_wait_status_busy(bank, 10);
838
839 if (retry > 10)
840 return ERROR_FLASH_OPERATION_FAILED;
841 else
842 {
843 i--;
844 retry++;
845 }
846 }
847 }
848 }
849
850 /* if the device doesn't support individual block lock bits set/clear,
851 * all blocks have been unlocked in parallel, so we set those that should be protected
852 */
853 if ((!set) && (!(pri_ext->feature_support & 0x20)))
854 {
855 for (i = 0; i < bank->num_sectors; i++)
856 {
857 if (bank->sectors[i].is_protected == 1)
858 {
859 cfi_intel_clear_status_register(bank);
860
861 cfi_command(bank, 0x60, command);
862 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
863
864 cfi_command(bank, 0x01, command);
865 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
866
867 cfi_intel_wait_status_busy(bank, 100);
868 }
869 }
870 }
871
872 cfi_command(bank, 0xff, command);
873 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
874
875 return ERROR_OK;
876 }
877
878 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
879 {
880 cfi_flash_bank_t *cfi_info = bank->driver_priv;
881
882 if (bank->target->state != TARGET_HALTED)
883 {
884 LOG_ERROR("Target not halted");
885 return ERROR_TARGET_NOT_HALTED;
886 }
887
888 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
889 {
890 return ERROR_FLASH_SECTOR_INVALID;
891 }
892
893 if (cfi_info->qry[0] != 'Q')
894 return ERROR_FLASH_BANK_NOT_PROBED;
895
896 switch(cfi_info->pri_id)
897 {
898 case 1:
899 case 3:
900 cfi_intel_protect(bank, set, first, last);
901 break;
902 default:
903 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
904 break;
905 }
906
907 return ERROR_OK;
908 }
909
910 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
911 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
912 {
913 /* target_t *target = bank->target; */
914
915 int i;
916
917 /* NOTE:
918 * The data to flash must not be changed in endian! We write a bytestrem in
919 * target byte order already. Only the control and status byte lane of the flash
920 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
921 * word (data seems to be in the upper or lower byte lane for u16 accesses).
922 */
923
924 #if 0
925 if (target->endianness == TARGET_LITTLE_ENDIAN)
926 {
927 #endif
928 /* shift bytes */
929 for (i = 0; i < bank->bus_width - 1; i++)
930 word[i] = word[i + 1];
931 word[bank->bus_width - 1] = byte;
932 #if 0
933 }
934 else
935 {
936 /* shift bytes */
937 for (i = bank->bus_width - 1; i > 0; i--)
938 word[i] = word[i - 1];
939 word[0] = byte;
940 }
941 #endif
942 }
943
944 /* Convert code image to target endian */
945 /* FIXME create general block conversion fcts in target.c?) */
946 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
947 {
948 u32 i;
949 for (i=0; i< count; i++)
950 {
951 target_buffer_set_u32(target, dest, *src);
952 dest+=4;
953 src++;
954 }
955 }
956
957 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
958 {
959 target_t *target = bank->target;
960
961 u8 buf[CFI_MAX_BUS_WIDTH];
962 cfi_command(bank, cmd, buf);
963 switch (bank->bus_width)
964 {
965 case 1 :
966 return buf[0];
967 break;
968 case 2 :
969 return target_buffer_get_u16(target, buf);
970 break;
971 case 4 :
972 return target_buffer_get_u32(target, buf);
973 break;
974 default :
975 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
976 return 0;
977 }
978 }
979
980 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
981 {
982 cfi_flash_bank_t *cfi_info = bank->driver_priv;
983 target_t *target = bank->target;
984 reg_param_t reg_params[7];
985 armv4_5_algorithm_t armv4_5_info;
986 working_area_t *source;
987 u32 buffer_size = 32768;
988 u32 write_command_val, busy_pattern_val, error_pattern_val;
989
990 /* algorithm register usage:
991 * r0: source address (in RAM)
992 * r1: target address (in Flash)
993 * r2: count
994 * r3: flash write command
995 * r4: status byte (returned to host)
996 * r5: busy test pattern
997 * r6: error test pattern
998 */
999
1000 static const u32 word_32_code[] = {
1001 0xe4904004, /* loop: ldr r4, [r0], #4 */
1002 0xe5813000, /* str r3, [r1] */
1003 0xe5814000, /* str r4, [r1] */
1004 0xe5914000, /* busy: ldr r4, [r1] */
1005 0xe0047005, /* and r7, r4, r5 */
1006 0xe1570005, /* cmp r7, r5 */
1007 0x1afffffb, /* bne busy */
1008 0xe1140006, /* tst r4, r6 */
1009 0x1a000003, /* bne done */
1010 0xe2522001, /* subs r2, r2, #1 */
1011 0x0a000001, /* beq done */
1012 0xe2811004, /* add r1, r1 #4 */
1013 0xeafffff2, /* b loop */
1014 0xeafffffe /* done: b -2 */
1015 };
1016
1017 static const u32 word_16_code[] = {
1018 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1019 0xe1c130b0, /* strh r3, [r1] */
1020 0xe1c140b0, /* strh r4, [r1] */
1021 0xe1d140b0, /* busy ldrh r4, [r1] */
1022 0xe0047005, /* and r7, r4, r5 */
1023 0xe1570005, /* cmp r7, r5 */
1024 0x1afffffb, /* bne busy */
1025 0xe1140006, /* tst r4, r6 */
1026 0x1a000003, /* bne done */
1027 0xe2522001, /* subs r2, r2, #1 */
1028 0x0a000001, /* beq done */
1029 0xe2811002, /* add r1, r1 #2 */
1030 0xeafffff2, /* b loop */
1031 0xeafffffe /* done: b -2 */
1032 };
1033
1034 static const u32 word_8_code[] = {
1035 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1036 0xe5c13000, /* strb r3, [r1] */
1037 0xe5c14000, /* strb r4, [r1] */
1038 0xe5d14000, /* busy ldrb r4, [r1] */
1039 0xe0047005, /* and r7, r4, r5 */
1040 0xe1570005, /* cmp r7, r5 */
1041 0x1afffffb, /* bne busy */
1042 0xe1140006, /* tst r4, r6 */
1043 0x1a000003, /* bne done */
1044 0xe2522001, /* subs r2, r2, #1 */
1045 0x0a000001, /* beq done */
1046 0xe2811001, /* add r1, r1 #1 */
1047 0xeafffff2, /* b loop */
1048 0xeafffffe /* done: b -2 */
1049 };
1050 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1051 const u32 *target_code_src;
1052 int target_code_size;
1053 int retval = ERROR_OK;
1054
1055
1056 cfi_intel_clear_status_register(bank);
1057
1058 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1059 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1060 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1061
1062 /* If we are setting up the write_algorith, we need target_code_src */
1063 /* if not we only need target_code_size. */
1064 /* */
1065 /* However, we don't want to create multiple code paths, so we */
1066 /* do the unecessary evaluation of target_code_src, which the */
1067 /* compiler will probably nicely optimize away if not needed */
1068
1069 /* prepare algorithm code for target endian */
1070 switch (bank->bus_width)
1071 {
1072 case 1 :
1073 target_code_src = word_8_code;
1074 target_code_size = sizeof(word_8_code);
1075 break;
1076 case 2 :
1077 target_code_src = word_16_code;
1078 target_code_size = sizeof(word_16_code);
1079 break;
1080 case 4 :
1081 target_code_src = word_32_code;
1082 target_code_size = sizeof(word_32_code);
1083 break;
1084 default:
1085 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1086 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1087 }
1088
1089 /* flash write code */
1090 if (!cfi_info->write_algorithm)
1091 {
1092 if ( target_code_size > sizeof(target_code) )
1093 {
1094 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1095 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1096 }
1097 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1098
1099 /* Get memory for block write handler */
1100 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1101 if (retval != ERROR_OK)
1102 {
1103 LOG_WARNING("No working area available, can't do block memory writes");
1104 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1105 };
1106
1107 /* write algorithm code to working area */
1108 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1109 if (retval != ERROR_OK)
1110 {
1111 LOG_ERROR("Unable to write block write code to target");
1112 goto cleanup;
1113 }
1114 }
1115
1116 /* Get a workspace buffer for the data to flash starting with 32k size.
1117 Half size until buffer would be smaller 256 Bytem then fail back */
1118 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1119 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1120 {
1121 buffer_size /= 2;
1122 if (buffer_size <= 256)
1123 {
1124 LOG_WARNING("no large enough working area available, can't do block memory writes");
1125 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126 goto cleanup;
1127 }
1128 };
1129
1130 /* setup algo registers */
1131 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1132 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1133 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1134 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1135 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1136 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1137 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1138
1139 /* prepare command and status register patterns */
1140 write_command_val = cfi_command_val(bank, 0x40);
1141 busy_pattern_val = cfi_command_val(bank, 0x80);
1142 error_pattern_val = cfi_command_val(bank, 0x7e);
1143
1144 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1145
1146 /* Programming main loop */
1147 while (count > 0)
1148 {
1149 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1150 u32 wsm_error;
1151
1152 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1153 {
1154 goto cleanup;
1155 }
1156
1157 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1158 buf_set_u32(reg_params[1].value, 0, 32, address);
1159 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1160
1161 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1162 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1163 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1164
1165 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1166
1167 /* Execute algorithm, assume breakpoint for last instruction */
1168 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1169 cfi_info->write_algorithm->address,
1170 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1171 10000, /* 10s should be enough for max. 32k of data */
1172 &armv4_5_info);
1173
1174 /* On failure try a fall back to direct word writes */
1175 if (retval != ERROR_OK)
1176 {
1177 cfi_intel_clear_status_register(bank);
1178 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1179 retval = ERROR_FLASH_OPERATION_FAILED;
1180 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1181 /* FIXME To allow fall back or recovery, we must save the actual status
1182 somewhere, so that a higher level code can start recovery. */
1183 goto cleanup;
1184 }
1185
1186 /* Check return value from algo code */
1187 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1188 if (wsm_error)
1189 {
1190 /* read status register (outputs debug inforation) */
1191 cfi_intel_wait_status_busy(bank, 100);
1192 cfi_intel_clear_status_register(bank);
1193 retval = ERROR_FLASH_OPERATION_FAILED;
1194 goto cleanup;
1195 }
1196
1197 buffer += thisrun_count;
1198 address += thisrun_count;
1199 count -= thisrun_count;
1200 }
1201
1202 /* free up resources */
1203 cleanup:
1204 if (source)
1205 target_free_working_area(target, source);
1206
1207 if (cfi_info->write_algorithm)
1208 {
1209 target_free_working_area(target, cfi_info->write_algorithm);
1210 cfi_info->write_algorithm = NULL;
1211 }
1212
1213 destroy_reg_param(&reg_params[0]);
1214 destroy_reg_param(&reg_params[1]);
1215 destroy_reg_param(&reg_params[2]);
1216 destroy_reg_param(&reg_params[3]);
1217 destroy_reg_param(&reg_params[4]);
1218 destroy_reg_param(&reg_params[5]);
1219 destroy_reg_param(&reg_params[6]);
1220
1221 return retval;
1222 }
1223
1224 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1225 {
1226 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1227 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1228 target_t *target = bank->target;
1229 reg_param_t reg_params[10];
1230 armv4_5_algorithm_t armv4_5_info;
1231 working_area_t *source;
1232 u32 buffer_size = 32768;
1233 u32 status;
1234 int retval, retvaltemp;
1235 int exit_code = ERROR_OK;
1236
1237 /* input parameters - */
1238 /* R0 = source address */
1239 /* R1 = destination address */
1240 /* R2 = number of writes */
1241 /* R3 = flash write command */
1242 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1243 /* output parameters - */
1244 /* R5 = 0x80 ok 0x00 bad */
1245 /* temp registers - */
1246 /* R6 = value read from flash to test status */
1247 /* R7 = holding register */
1248 /* unlock registers - */
1249 /* R8 = unlock1_addr */
1250 /* R9 = unlock1_cmd */
1251 /* R10 = unlock2_addr */
1252 /* R11 = unlock2_cmd */
1253
1254 static const u32 word_32_code[] = {
1255 /* 00008100 <sp_32_code>: */
1256 0xe4905004, /* ldr r5, [r0], #4 */
1257 0xe5889000, /* str r9, [r8] */
1258 0xe58ab000, /* str r11, [r10] */
1259 0xe5883000, /* str r3, [r8] */
1260 0xe5815000, /* str r5, [r1] */
1261 0xe1a00000, /* nop */
1262 /* */
1263 /* 00008110 <sp_32_busy>: */
1264 0xe5916000, /* ldr r6, [r1] */
1265 0xe0257006, /* eor r7, r5, r6 */
1266 0xe0147007, /* ands r7, r4, r7 */
1267 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1268 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1269 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1270 0xe5916000, /* ldr r6, [r1] */
1271 0xe0257006, /* eor r7, r5, r6 */
1272 0xe0147007, /* ands r7, r4, r7 */
1273 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1274 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1275 0x1a000004, /* bne 8154 <sp_32_done> */
1276 /* */
1277 /* 00008140 <sp_32_cont>: */
1278 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1279 0x03a05080, /* moveq r5, #128 ; 0x80 */
1280 0x0a000001, /* beq 8154 <sp_32_done> */
1281 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1282 0xeaffffe8, /* b 8100 <sp_32_code> */
1283 /* */
1284 /* 00008154 <sp_32_done>: */
1285 0xeafffffe /* b 8154 <sp_32_done> */
1286 };
1287
1288 static const u32 word_16_code[] = {
1289 /* 00008158 <sp_16_code>: */
1290 0xe0d050b2, /* ldrh r5, [r0], #2 */
1291 0xe1c890b0, /* strh r9, [r8] */
1292 0xe1cab0b0, /* strh r11, [r10] */
1293 0xe1c830b0, /* strh r3, [r8] */
1294 0xe1c150b0, /* strh r5, [r1] */
1295 0xe1a00000, /* nop (mov r0,r0) */
1296 /* */
1297 /* 00008168 <sp_16_busy>: */
1298 0xe1d160b0, /* ldrh r6, [r1] */
1299 0xe0257006, /* eor r7, r5, r6 */
1300 0xe0147007, /* ands r7, r4, r7 */
1301 0x0a000007, /* beq 8198 <sp_16_cont> */
1302 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1303 0x0afffff9, /* beq 8168 <sp_16_busy> */
1304 0xe1d160b0, /* ldrh r6, [r1] */
1305 0xe0257006, /* eor r7, r5, r6 */
1306 0xe0147007, /* ands r7, r4, r7 */
1307 0x0a000001, /* beq 8198 <sp_16_cont> */
1308 0xe3a05000, /* mov r5, #0 ; 0x0 */
1309 0x1a000004, /* bne 81ac <sp_16_done> */
1310 /* */
1311 /* 00008198 <sp_16_cont>: */
1312 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1313 0x03a05080, /* moveq r5, #128 ; 0x80 */
1314 0x0a000001, /* beq 81ac <sp_16_done> */
1315 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1316 0xeaffffe8, /* b 8158 <sp_16_code> */
1317 /* */
1318 /* 000081ac <sp_16_done>: */
1319 0xeafffffe /* b 81ac <sp_16_done> */
1320 };
1321
1322 static const u32 word_8_code[] = {
1323 /* 000081b0 <sp_16_code_end>: */
1324 0xe4d05001, /* ldrb r5, [r0], #1 */
1325 0xe5c89000, /* strb r9, [r8] */
1326 0xe5cab000, /* strb r11, [r10] */
1327 0xe5c83000, /* strb r3, [r8] */
1328 0xe5c15000, /* strb r5, [r1] */
1329 0xe1a00000, /* nop (mov r0,r0) */
1330 /* */
1331 /* 000081c0 <sp_8_busy>: */
1332 0xe5d16000, /* ldrb r6, [r1] */
1333 0xe0257006, /* eor r7, r5, r6 */
1334 0xe0147007, /* ands r7, r4, r7 */
1335 0x0a000007, /* beq 81f0 <sp_8_cont> */
1336 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1337 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1338 0xe5d16000, /* ldrb r6, [r1] */
1339 0xe0257006, /* eor r7, r5, r6 */
1340 0xe0147007, /* ands r7, r4, r7 */
1341 0x0a000001, /* beq 81f0 <sp_8_cont> */
1342 0xe3a05000, /* mov r5, #0 ; 0x0 */
1343 0x1a000004, /* bne 8204 <sp_8_done> */
1344 /* */
1345 /* 000081f0 <sp_8_cont>: */
1346 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1347 0x03a05080, /* moveq r5, #128 ; 0x80 */
1348 0x0a000001, /* beq 8204 <sp_8_done> */
1349 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1350 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1351 /* */
1352 /* 00008204 <sp_8_done>: */
1353 0xeafffffe /* b 8204 <sp_8_done> */
1354 };
1355
1356 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1357 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1358 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1359
1360 /* flash write code */
1361 if (!cfi_info->write_algorithm)
1362 {
1363 u8 *target_code;
1364 int target_code_size;
1365 const u32 *src;
1366
1367 /* convert bus-width dependent algorithm code to correct endiannes */
1368 switch (bank->bus_width)
1369 {
1370 case 1:
1371 src = word_8_code;
1372 target_code_size = sizeof(word_8_code);
1373 break;
1374 case 2:
1375 src = word_16_code;
1376 target_code_size = sizeof(word_16_code);
1377 break;
1378 case 4:
1379 src = word_32_code;
1380 target_code_size = sizeof(word_32_code);
1381 break;
1382 default:
1383 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1384 return ERROR_FLASH_OPERATION_FAILED;
1385 }
1386 target_code = malloc(target_code_size);
1387 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1388
1389 /* allocate working area */
1390 retval=target_alloc_working_area(target, target_code_size,
1391 &cfi_info->write_algorithm);
1392 if (retval != ERROR_OK)
1393 {
1394 free(target_code);
1395 return retval;
1396 }
1397
1398 /* write algorithm code to working area */
1399 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1400 target_code_size, target_code)) != ERROR_OK)
1401 {
1402 free(target_code);
1403 return retval;
1404 }
1405
1406 free(target_code);
1407 }
1408 /* the following code still assumes target code is fixed 24*4 bytes */
1409
1410 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1411 {
1412 buffer_size /= 2;
1413 if (buffer_size <= 256)
1414 {
1415 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1416 if (cfi_info->write_algorithm)
1417 target_free_working_area(target, cfi_info->write_algorithm);
1418
1419 LOG_WARNING("not enough working area available, can't do block memory writes");
1420 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1421 }
1422 };
1423
1424 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1425 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1426 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1427 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1428 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1429 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1430 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1431 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1432 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1433 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1434
1435 while (count > 0)
1436 {
1437 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1438
1439 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1440
1441 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1442 buf_set_u32(reg_params[1].value, 0, 32, address);
1443 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1444 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1445 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1446 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1447 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1448 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1449 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1450
1451 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1452 cfi_info->write_algorithm->address,
1453 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1454 10000, &armv4_5_info);
1455
1456 status = buf_get_u32(reg_params[5].value, 0, 32);
1457
1458 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1459 {
1460 LOG_DEBUG("status: 0x%x", status);
1461 exit_code = ERROR_FLASH_OPERATION_FAILED;
1462 break;
1463 }
1464
1465 buffer += thisrun_count;
1466 address += thisrun_count;
1467 count -= thisrun_count;
1468 }
1469
1470 target_free_working_area(target, source);
1471
1472 destroy_reg_param(&reg_params[0]);
1473 destroy_reg_param(&reg_params[1]);
1474 destroy_reg_param(&reg_params[2]);
1475 destroy_reg_param(&reg_params[3]);
1476 destroy_reg_param(&reg_params[4]);
1477 destroy_reg_param(&reg_params[5]);
1478 destroy_reg_param(&reg_params[6]);
1479 destroy_reg_param(&reg_params[7]);
1480 destroy_reg_param(&reg_params[8]);
1481 destroy_reg_param(&reg_params[9]);
1482
1483 return exit_code;
1484 }
1485
1486 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1487 {
1488 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1489 target_t *target = bank->target;
1490 u8 command[8];
1491
1492 cfi_intel_clear_status_register(bank);
1493 cfi_command(bank, 0x40, command);
1494 target->type->write_memory(target, address, bank->bus_width, 1, command);
1495
1496 target->type->write_memory(target, address, bank->bus_width, 1, word);
1497
1498 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1499 {
1500 cfi_command(bank, 0xff, command);
1501 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1502
1503 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1504 return ERROR_FLASH_OPERATION_FAILED;
1505 }
1506
1507 return ERROR_OK;
1508 }
1509
1510 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1511 {
1512 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1513 target_t *target = bank->target;
1514 u8 command[8];
1515
1516 /* Calculate buffer size and boundary mask */
1517 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1518 u32 buffermask = buffersize-1;
1519 u32 bufferwsize;
1520
1521 /* Check for valid range */
1522 if (address & buffermask)
1523 {
1524 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1525 return ERROR_FLASH_OPERATION_FAILED;
1526 }
1527 switch(bank->chip_width)
1528 {
1529 case 4 : bufferwsize = buffersize / 4; break;
1530 case 2 : bufferwsize = buffersize / 2; break;
1531 case 1 : bufferwsize = buffersize; break;
1532 default:
1533 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1534 return ERROR_FLASH_OPERATION_FAILED;
1535 }
1536
1537 /* Check for valid size */
1538 if (wordcount > bufferwsize)
1539 {
1540 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1541 return ERROR_FLASH_OPERATION_FAILED;
1542 }
1543
1544 /* Write to flash buffer */
1545 cfi_intel_clear_status_register(bank);
1546
1547 /* Initiate buffer operation _*/
1548 cfi_command(bank, 0xE8, command);
1549 target->type->write_memory(target, address, bank->bus_width, 1, command);
1550 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1551 {
1552 cfi_command(bank, 0xff, command);
1553 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1554
1555 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1556 return ERROR_FLASH_OPERATION_FAILED;
1557 }
1558
1559 /* Write buffer wordcount-1 and data words */
1560 cfi_command(bank, bufferwsize-1, command);
1561 target->type->write_memory(target, address, bank->bus_width, 1, command);
1562
1563 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1564
1565 /* Commit write operation */
1566 cfi_command(bank, 0xd0, command);
1567 target->type->write_memory(target, address, bank->bus_width, 1, command);
1568 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1569 {
1570 cfi_command(bank, 0xff, command);
1571 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1572
1573 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1574 return ERROR_FLASH_OPERATION_FAILED;
1575 }
1576
1577 return ERROR_OK;
1578 }
1579
1580 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1581 {
1582 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1583 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1584 target_t *target = bank->target;
1585 u8 command[8];
1586
1587 cfi_command(bank, 0xaa, command);
1588 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1589
1590 cfi_command(bank, 0x55, command);
1591 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1592
1593 cfi_command(bank, 0xa0, command);
1594 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1595
1596 target->type->write_memory(target, address, bank->bus_width, 1, word);
1597
1598 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1599 {
1600 cfi_command(bank, 0xf0, command);
1601 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1602
1603 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1604 return ERROR_FLASH_OPERATION_FAILED;
1605 }
1606
1607 return ERROR_OK;
1608 }
1609
1610 int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1611 {
1612 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1613 target_t *target = bank->target;
1614 u8 command[8];
1615 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1616
1617 /* Calculate buffer size and boundary mask */
1618 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1619 u32 buffermask = buffersize-1;
1620 u32 bufferwsize;
1621
1622 /* Check for valid range */
1623 if (address & buffermask)
1624 {
1625 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1626 return ERROR_FLASH_OPERATION_FAILED;
1627 }
1628 switch(bank->chip_width)
1629 {
1630 case 4 : bufferwsize = buffersize / 4; break;
1631 case 2 : bufferwsize = buffersize / 2; break;
1632 case 1 : bufferwsize = buffersize; break;
1633 default:
1634 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1635 return ERROR_FLASH_OPERATION_FAILED;
1636 }
1637
1638 /* Check for valid size */
1639 if (wordcount > bufferwsize)
1640 {
1641 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1642 return ERROR_FLASH_OPERATION_FAILED;
1643 }
1644
1645 // Unlock
1646 cfi_command(bank, 0xaa, command);
1647 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1648
1649 cfi_command(bank, 0x55, command);
1650 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1651
1652 // Buffer load command
1653 cfi_command(bank, 0x25, command);
1654 target->type->write_memory(target, address, bank->bus_width, 1, command);
1655
1656 /* Write buffer wordcount-1 and data words */
1657 cfi_command(bank, bufferwsize-1, command);
1658 target->type->write_memory(target, address, bank->bus_width, 1, command);
1659
1660 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1661
1662 /* Commit write operation */
1663 cfi_command(bank, 0x29, command);
1664 target->type->write_memory(target, address, bank->bus_width, 1, command);
1665
1666 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1667 {
1668 cfi_command(bank, 0xf0, command);
1669 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1670
1671 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1672 return ERROR_FLASH_OPERATION_FAILED;
1673 }
1674
1675 return ERROR_OK;
1676 }
1677
1678 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1679 {
1680 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1681
1682 switch(cfi_info->pri_id)
1683 {
1684 case 1:
1685 case 3:
1686 return cfi_intel_write_word(bank, word, address);
1687 break;
1688 case 2:
1689 return cfi_spansion_write_word(bank, word, address);
1690 break;
1691 default:
1692 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1693 break;
1694 }
1695
1696 return ERROR_FLASH_OPERATION_FAILED;
1697 }
1698
1699 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1700 {
1701 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1702
1703 switch(cfi_info->pri_id)
1704 {
1705 case 1:
1706 case 3:
1707 return cfi_intel_write_words(bank, word, wordcount, address);
1708 break;
1709 case 2:
1710 return cfi_spansion_write_words(bank, word, wordcount, address);
1711 break;
1712 default:
1713 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1714 break;
1715 }
1716
1717 return ERROR_FLASH_OPERATION_FAILED;
1718 }
1719
1720 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1721 {
1722 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1723 target_t *target = bank->target;
1724 u32 address = bank->base + offset; /* address of first byte to be programmed */
1725 u32 write_p, copy_p;
1726 int align; /* number of unaligned bytes */
1727 int blk_count; /* number of bus_width bytes for block copy */
1728 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1729 int i;
1730 int retval;
1731
1732 if (bank->target->state != TARGET_HALTED)
1733 {
1734 LOG_ERROR("Target not halted");
1735 return ERROR_TARGET_NOT_HALTED;
1736 }
1737
1738 if (offset + count > bank->size)
1739 return ERROR_FLASH_DST_OUT_OF_BANK;
1740
1741 if (cfi_info->qry[0] != 'Q')
1742 return ERROR_FLASH_BANK_NOT_PROBED;
1743
1744 /* start at the first byte of the first word (bus_width size) */
1745 write_p = address & ~(bank->bus_width - 1);
1746 if ((align = address - write_p) != 0)
1747 {
1748 LOG_INFO("Fixup %d unaligned head bytes", align );
1749
1750 for (i = 0; i < bank->bus_width; i++)
1751 current_word[i] = 0;
1752 copy_p = write_p;
1753
1754 /* copy bytes before the first write address */
1755 for (i = 0; i < align; ++i, ++copy_p)
1756 {
1757 u8 byte;
1758 target->type->read_memory(target, copy_p, 1, 1, &byte);
1759 cfi_add_byte(bank, current_word, byte);
1760 }
1761
1762 /* add bytes from the buffer */
1763 for (; (i < bank->bus_width) && (count > 0); i++)
1764 {
1765 cfi_add_byte(bank, current_word, *buffer++);
1766 count--;
1767 copy_p++;
1768 }
1769
1770 /* if the buffer is already finished, copy bytes after the last write address */
1771 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1772 {
1773 u8 byte;
1774 target->type->read_memory(target, copy_p, 1, 1, &byte);
1775 cfi_add_byte(bank, current_word, byte);
1776 }
1777
1778 retval = cfi_write_word(bank, current_word, write_p);
1779 if (retval != ERROR_OK)
1780 return retval;
1781 write_p = copy_p;
1782 }
1783
1784 /* handle blocks of bus_size aligned bytes */
1785 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1786 switch(cfi_info->pri_id)
1787 {
1788 /* try block writes (fails without working area) */
1789 case 1:
1790 case 3:
1791 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1792 break;
1793 case 2:
1794 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1795 break;
1796 default:
1797 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1798 retval = ERROR_FLASH_OPERATION_FAILED;
1799 break;
1800 }
1801 if (retval == ERROR_OK)
1802 {
1803 /* Increment pointers and decrease count on succesful block write */
1804 buffer += blk_count;
1805 write_p += blk_count;
1806 count -= blk_count;
1807 }
1808 else
1809 {
1810 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1811 {
1812 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1813 u32 buffermask = buffersize-1;
1814 u32 bufferwsize;
1815
1816 switch(bank->chip_width)
1817 {
1818 case 4 : bufferwsize = buffersize / 4; break;
1819 case 2 : bufferwsize = buffersize / 2; break;
1820 case 1 : bufferwsize = buffersize; break;
1821 default:
1822 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1823 return ERROR_FLASH_OPERATION_FAILED;
1824 }
1825
1826 /* fall back to memory writes */
1827 while (count >= bank->bus_width)
1828 {
1829 int fallback;
1830 if ((write_p & 0xff) == 0)
1831 {
1832 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1833 }
1834 fallback = 1;
1835 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1836 {
1837 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1838 if (retval == ERROR_OK)
1839 {
1840 buffer += buffersize;
1841 write_p += buffersize;
1842 count -= buffersize;
1843 fallback=0;
1844 }
1845 }
1846 /* try the slow way? */
1847 if (fallback)
1848 {
1849 for (i = 0; i < bank->bus_width; i++)
1850 current_word[i] = 0;
1851
1852 for (i = 0; i < bank->bus_width; i++)
1853 {
1854 cfi_add_byte(bank, current_word, *buffer++);
1855 }
1856
1857 retval = cfi_write_word(bank, current_word, write_p);
1858 if (retval != ERROR_OK)
1859 return retval;
1860
1861 write_p += bank->bus_width;
1862 count -= bank->bus_width;
1863 }
1864 }
1865 }
1866 else
1867 return retval;
1868 }
1869
1870 /* return to read array mode, so we can read from flash again for padding */
1871 cfi_command(bank, 0xf0, current_word);
1872 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1873 cfi_command(bank, 0xff, current_word);
1874 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1875
1876 /* handle unaligned tail bytes */
1877 if (count > 0)
1878 {
1879 LOG_INFO("Fixup %d unaligned tail bytes", count );
1880
1881 copy_p = write_p;
1882 for (i = 0; i < bank->bus_width; i++)
1883 current_word[i] = 0;
1884
1885 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1886 {
1887 cfi_add_byte(bank, current_word, *buffer++);
1888 count--;
1889 }
1890 for (; i < bank->bus_width; ++i, ++copy_p)
1891 {
1892 u8 byte;
1893 target->type->read_memory(target, copy_p, 1, 1, &byte);
1894 cfi_add_byte(bank, current_word, byte);
1895 }
1896 retval = cfi_write_word(bank, current_word, write_p);
1897 if (retval != ERROR_OK)
1898 return retval;
1899 }
1900
1901 /* return to read array mode */
1902 cfi_command(bank, 0xf0, current_word);
1903 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1904 cfi_command(bank, 0xff, current_word);
1905 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1906
1907 return ERROR_OK;
1908 }
1909
1910 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1911 {
1912 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1913 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1914
1915 pri_ext->_reversed_geometry = 1;
1916 }
1917
1918 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1919 {
1920 int i;
1921 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1922 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1923
1924 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1925 {
1926 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1927
1928 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1929 {
1930 int j = (cfi_info->num_erase_regions - 1) - i;
1931 u32 swap;
1932
1933 swap = cfi_info->erase_region_info[i];
1934 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1935 cfi_info->erase_region_info[j] = swap;
1936 }
1937 }
1938 }
1939
1940 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1941 {
1942 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1943 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1944 cfi_unlock_addresses_t *unlock_addresses = param;
1945
1946 pri_ext->_unlock1 = unlock_addresses->unlock1;
1947 pri_ext->_unlock2 = unlock_addresses->unlock2;
1948 }
1949
1950 int cfi_probe(struct flash_bank_s *bank)
1951 {
1952 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1953 target_t *target = bank->target;
1954 u8 command[8];
1955 int num_sectors = 0;
1956 int i;
1957 int sector = 0;
1958 u32 offset = 0;
1959 u32 unlock1 = 0x555;
1960 u32 unlock2 = 0x2aa;
1961 int retval;
1962
1963 if (bank->target->state != TARGET_HALTED)
1964 {
1965 LOG_ERROR("Target not halted");
1966 return ERROR_TARGET_NOT_HALTED;
1967 }
1968
1969 cfi_info->probed = 0;
1970
1971 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1972 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1973 */
1974 if (cfi_info->jedec_probe)
1975 {
1976 unlock1 = 0x5555;
1977 unlock2 = 0x2aaa;
1978 }
1979
1980 /* switch to read identifier codes mode ("AUTOSELECT") */
1981 cfi_command(bank, 0xaa, command);
1982 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1983 cfi_command(bank, 0x55, command);
1984 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1985 cfi_command(bank, 0x90, command);
1986 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1987
1988 if (bank->chip_width == 1)
1989 {
1990 u8 manufacturer, device_id;
1991 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
1992 {
1993 return retval;
1994 }
1995 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
1996 {
1997 return retval;
1998 }
1999 cfi_info->manufacturer = manufacturer;
2000 cfi_info->device_id = device_id;
2001 }
2002 else if (bank->chip_width == 2)
2003 {
2004 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2005 {
2006 return retval;
2007 }
2008 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2009 {
2010 return retval;
2011 }
2012 }
2013
2014 /* switch back to read array mode */
2015 cfi_command(bank, 0xf0, command);
2016 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
2017 cfi_command(bank, 0xff, command);
2018 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
2019
2020 cfi_fixup(bank, cfi_jedec_fixups);
2021
2022 /* query only if this is a CFI compatible flash,
2023 * otherwise the relevant info has already been filled in
2024 */
2025 if (cfi_info->not_cfi == 0)
2026 {
2027 /* enter CFI query mode
2028 * according to JEDEC Standard No. 68.01,
2029 * a single bus sequence with address = 0x55, data = 0x98 should put
2030 * the device into CFI query mode.
2031 *
2032 * SST flashes clearly violate this, and we will consider them incompatbile for now
2033 */
2034 cfi_command(bank, 0x98, command);
2035 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2036
2037 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2038 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2039 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2040
2041 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2042
2043 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2044 {
2045 cfi_command(bank, 0xf0, command);
2046 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2047 cfi_command(bank, 0xff, command);
2048 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2049 LOG_ERROR("Could not probe bank");
2050 return ERROR_FLASH_BANK_INVALID;
2051 }
2052
2053 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2054 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2055 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2056 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2057
2058 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2059
2060 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2061 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2062 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2063 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2064 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2065 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2066 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2067 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2068 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2069 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2070 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2071 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2072
2073 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2074 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2075 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2076 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2077 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2078 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2079 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2080 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2081 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2082 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2083 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2084
2085 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
2086 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2087 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2088 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2089
2090 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2091
2092 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
2093 {
2094 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
2095 }
2096
2097 if (cfi_info->num_erase_regions)
2098 {
2099 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2100 for (i = 0; i < cfi_info->num_erase_regions; i++)
2101 {
2102 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2103 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2104 }
2105 }
2106 else
2107 {
2108 cfi_info->erase_region_info = NULL;
2109 }
2110
2111 /* We need to read the primary algorithm extended query table before calculating
2112 * the sector layout to be able to apply fixups
2113 */
2114 switch(cfi_info->pri_id)
2115 {
2116 /* Intel command set (standard and extended) */
2117 case 0x0001:
2118 case 0x0003:
2119 cfi_read_intel_pri_ext(bank);
2120 break;
2121 /* AMD/Spansion, Atmel, ... command set */
2122 case 0x0002:
2123 cfi_read_0002_pri_ext(bank);
2124 break;
2125 default:
2126 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2127 break;
2128 }
2129
2130 /* return to read array mode
2131 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2132 */
2133 cfi_command(bank, 0xf0, command);
2134 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2135 cfi_command(bank, 0xff, command);
2136 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2137 }
2138
2139 /* apply fixups depending on the primary command set */
2140 switch(cfi_info->pri_id)
2141 {
2142 /* Intel command set (standard and extended) */
2143 case 0x0001:
2144 case 0x0003:
2145 cfi_fixup(bank, cfi_0001_fixups);
2146 break;
2147 /* AMD/Spansion, Atmel, ... command set */
2148 case 0x0002:
2149 cfi_fixup(bank, cfi_0002_fixups);
2150 break;
2151 default:
2152 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2153 break;
2154 }
2155
2156 if (cfi_info->num_erase_regions == 0)
2157 {
2158 /* a device might have only one erase block, spanning the whole device */
2159 bank->num_sectors = 1;
2160 bank->sectors = malloc(sizeof(flash_sector_t));
2161
2162 bank->sectors[sector].offset = 0x0;
2163 bank->sectors[sector].size = bank->size;
2164 bank->sectors[sector].is_erased = -1;
2165 bank->sectors[sector].is_protected = -1;
2166 }
2167 else
2168 {
2169 for (i = 0; i < cfi_info->num_erase_regions; i++)
2170 {
2171 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2172 }
2173
2174 bank->num_sectors = num_sectors;
2175 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2176
2177 for (i = 0; i < cfi_info->num_erase_regions; i++)
2178 {
2179 int j;
2180 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2181 {
2182 bank->sectors[sector].offset = offset;
2183 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2184 offset += bank->sectors[sector].size;
2185 bank->sectors[sector].is_erased = -1;
2186 bank->sectors[sector].is_protected = -1;
2187 sector++;
2188 }
2189 }
2190 }
2191
2192 cfi_info->probed = 1;
2193
2194 return ERROR_OK;
2195 }
2196
2197 int cfi_auto_probe(struct flash_bank_s *bank)
2198 {
2199 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2200 if (cfi_info->probed)
2201 return ERROR_OK;
2202 return cfi_probe(bank);
2203 }
2204
2205
2206 int cfi_intel_protect_check(struct flash_bank_s *bank)
2207 {
2208 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2209 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2210 target_t *target = bank->target;
2211 u8 command[CFI_MAX_BUS_WIDTH];
2212 int i;
2213
2214 /* check if block lock bits are supported on this device */
2215 if (!(pri_ext->blk_status_reg_mask & 0x1))
2216 return ERROR_FLASH_OPERATION_FAILED;
2217
2218 cfi_command(bank, 0x90, command);
2219 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2220
2221 for (i = 0; i < bank->num_sectors; i++)
2222 {
2223 u8 block_status = cfi_get_u8(bank, i, 0x2);
2224
2225 if (block_status & 1)
2226 bank->sectors[i].is_protected = 1;
2227 else
2228 bank->sectors[i].is_protected = 0;
2229 }
2230
2231 cfi_command(bank, 0xff, command);
2232 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2233
2234 return ERROR_OK;
2235 }
2236
2237 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2238 {
2239 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2240 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2241 target_t *target = bank->target;
2242 u8 command[8];
2243 int i;
2244
2245 cfi_command(bank, 0xaa, command);
2246 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2247
2248 cfi_command(bank, 0x55, command);
2249 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2250
2251 cfi_command(bank, 0x90, command);
2252 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2253
2254 for (i = 0; i < bank->num_sectors; i++)
2255 {
2256 u8 block_status = cfi_get_u8(bank, i, 0x2);
2257
2258 if (block_status & 1)
2259 bank->sectors[i].is_protected = 1;
2260 else
2261 bank->sectors[i].is_protected = 0;
2262 }
2263
2264 cfi_command(bank, 0xf0, command);
2265 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2266
2267 return ERROR_OK;
2268 }
2269
2270 int cfi_protect_check(struct flash_bank_s *bank)
2271 {
2272 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2273
2274 if (bank->target->state != TARGET_HALTED)
2275 {
2276 LOG_ERROR("Target not halted");
2277 return ERROR_TARGET_NOT_HALTED;
2278 }
2279
2280 if (cfi_info->qry[0] != 'Q')
2281 return ERROR_FLASH_BANK_NOT_PROBED;
2282
2283 switch(cfi_info->pri_id)
2284 {
2285 case 1:
2286 case 3:
2287 return cfi_intel_protect_check(bank);
2288 break;
2289 case 2:
2290 return cfi_spansion_protect_check(bank);
2291 break;
2292 default:
2293 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2294 break;
2295 }
2296
2297 return ERROR_OK;
2298 }
2299
2300 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2301 {
2302 int printed;
2303 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2304
2305 if (cfi_info->qry[0] == (char)-1)
2306 {
2307 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2308 return ERROR_OK;
2309 }
2310
2311 if (cfi_info->not_cfi == 0)
2312 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2313 else
2314 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2315 buf += printed;
2316 buf_size -= printed;
2317
2318 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2319 cfi_info->manufacturer, cfi_info->device_id);
2320 buf += printed;
2321 buf_size -= printed;
2322
2323 if (cfi_info->not_cfi == 0)
2324 {
2325 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2326 buf += printed;
2327 buf_size -= printed;
2328
2329 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2330 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2331 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2332 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2333 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2334 buf += printed;
2335 buf_size -= printed;
2336
2337 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2338 1 << cfi_info->word_write_timeout_typ,
2339 1 << cfi_info->buf_write_timeout_typ,
2340 1 << cfi_info->block_erase_timeout_typ,
2341 1 << cfi_info->chip_erase_timeout_typ);
2342 buf += printed;
2343 buf_size -= printed;
2344
2345 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2346 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2347 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2348 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2349 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2350 buf += printed;
2351 buf_size -= printed;
2352
2353 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2354 1 << cfi_info->dev_size,
2355 cfi_info->interface_desc,
2356 1 << cfi_info->max_buf_write_size);
2357 buf += printed;
2358 buf_size -= printed;
2359
2360 switch(cfi_info->pri_id)
2361 {
2362 case 1:
2363 case 3:
2364 cfi_intel_info(bank, buf, buf_size);
2365 break;
2366 case 2:
2367 cfi_spansion_info(bank, buf, buf_size);
2368 break;
2369 default:
2370 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2371 break;
2372 }
2373 }
2374
2375 return ERROR_OK;
2376 }
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