testing/examples/STR710JtagSpeed/src/crt.s

   1 /****************************************************************************
   2 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
   3 *
   4 *  Redistribution and use in source and binary forms, with or without
   5 *  modification, are permitted provided that the following conditions
   6 *  are met:
   7 *
   8 *  1. Redistributions of source code must retain the above copyright
   9 *     notice, this list of conditions and the following disclaimer.
  10 *  2. Redistributions in binary form must reproduce the above copyright
  11 *     notice, this list of conditions and the following disclaimer in the
  12 *     documentation and/or other materials provided with the distribution.
  13 *  3. Neither the name of the author nor the names of its contributors may
  14 *     be used to endorse or promote products derived from this software
  15 *     without specific prior written permission.
  16 *
  17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20 *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21 *  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25 *  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26 *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27 *  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28 *  SUCH DAMAGE.
  29 *
  30 ****************************************************************************
  31 *
  32 *  History:
  33 *
  34 *  04.03.06  mifi   First Version
  35 *                   This version based on an example from Ethernut and
  36 *                   "ARM Cross Development with Eclipse" from James P. Lynch
  37 ****************************************************************************/
  38
  39 /*
  40  * Some defines for the program status registers
  41  */
  42    ARM_MODE_USER  = 0x10      /* Normal User Mode                                                      */
  43    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                                        */
  44    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                            */
  45    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                              */
  46    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode               */
  47    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                        */
  48    ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
  49    ARM_MODE_MASK  = 0x1F
  50
  51    I_BIT          = 0x80      /* disable IRQ when I bit is set */
  52    F_BIT          = 0x40      /* disable IRQ when I bit is set */
  53
  54 /*
  55  * Register Base Address
  56  */
  57    PRCCU_BASE     = 0xA0000000
  58    RCCU_CFR       = 0x08
  59    RCCU_PLL1CR    = 0x18
  60    PCU_MDIVR      = 0x40
  61    PCU_PDIVR      = 0x44
  62    PCU_BOOTCR     = 0x50
  63
  64
  65
  66
  67    .section .vectors,"ax"
  68    .code 32
  69
  70 /****************************************************************************/
  71 /*               Vector table and reset entry                               */
  72 /****************************************************************************/
  73 _vectors:
  74    ldr pc, ResetAddr    /* Reset                 */
  75    ldr pc, UndefAddr    /* Undefined instruction */
  76    ldr pc, SWIAddr      /* Software interrupt    */
  77    ldr pc, PAbortAddr   /* Prefetch abort        */
  78    ldr pc, DAbortAddr   /* Data abort            */
  79    ldr pc, ReservedAddr /* Reserved              */
  80    ldr pc, IRQAddr      /* IRQ interrupt         */
  81    ldr pc, FIQAddr      /* FIQ interrupt         */
  82
  83
  84 ResetAddr:     .word ResetHandler
  85 UndefAddr:     .word UndefHandler
  86 SWIAddr:       .word SWIHandler
  87 PAbortAddr:    .word PAbortHandler
  88 DAbortAddr:    .word DAbortHandler
  89 ReservedAddr:  .word 0
  90 IRQAddr:       .word IRQHandler
  91 FIQAddr:       .word FIQHandler
  92
  93    .ltorg
  94
  95
  96    .section .init, "ax"
  97    .code 32
  98
  99    .global ResetHandler
 100    .global ExitFunction
 101    .extern main
 102 /****************************************************************************/
 103 /*                           Reset handler                                  */
 104 /****************************************************************************/
 105 ResetHandler:
 106 /*
 107  * Wait for the oscillator is stable
 108  */
 109    nop
 110    nop
 111    nop
 112    nop
 113    nop
 114    nop
 115    nop
 116    nop
 117
 118 /*
 119  * Setup STR71X, for more information about the register
 120  * take a look in the STR71x Microcontroller Reference Manual.
 121  *
 122  * Reference is made to: Rev. 6 March 2005
 123  *
 124  * 1. Map internal RAM to address 0
 125  *    In this case, we are running always in the RAM
 126  *    this make no sence. But if we are in flash, we
 127  *    can copy the interrupt vectors into the ram and
 128  *    switch to RAM mode.
 129  *
 130  * 2. Setup the PLL, the eval board HITEX STR7 is equipped
 131  *    with an external 16MHz oscillator. We want:
 132  *
 133  *    RCLK:  32MHz = (CLK2 * 16) / 4
 134  *    MCLK:  32Mhz
 135  *    PCLK1: 32MHz
 136  *    PCLK2: 32MHz
 137  *
 138  */
 139
 140    /*
 141     * 1. Map RAM to the boot memory 0x00000000
 142     */
 143    ldr   r0, =PRCCU_BASE
 144    ldr   r1, =0x01C2
 145    str   r1, [r0, #PCU_BOOTCR]
 146
 147
 148    /*
 149     * 2. Setup PLL start
 150     */
 151
 152    /* Set the prescaling factor for APB and APB1 group */
 153    ldr   r0, =PRCCU_BASE
 154    ldr   r1, =0x0000             /* no prescaling PCLKx = RCLK */
 155    str   r1, [r0, #PCU_PDIVR]
 156
 157    /* Set the prescaling factor for the Main System Clock MCLK */
 158    ldr   r0, =PRCCU_BASE
 159    ldr   r1, =0x0000             /* no prescaling MCLK = RCLK
 160    str   r1, [r0, #PCU_MDIVR]
 161
 162    /* Configure the PLL1 ( * 16 , / 4 ) */
 163    ldr   r0, =PRCCU_BASE
 164    ldr   r1, =0x0073
 165    str   r1, [r0, #RCCU_PLL1CR]
 166
 167    /* Check if the PLL is locked */
 168 pll_lock_loop:
 169    ldr   r1, [r0, #RCCU_CFR]
 170    tst   r1, #0x0002
 171    beq   pll_lock_loop
 172
 173    /*  Select PLL1_Output as RCLK clock */
 174    ldr   r0, =PRCCU_BASE
 175    ldr   r1, =0x8009
 176    str   r1, [r0, #RCCU_CFR]
 177
 178    /*
 179     * Setup PLL end
 180     */
 181
 182
 183    /*
 184     * Setup a stack for each mode
 185     */
 186    msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
 187    ldr   sp, =__stack_und_end
 188
 189    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
 190    ldr   sp, =__stack_abt_end
 191
 192    msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
 193    ldr   sp, =__stack_fiq_end
 194
 195    msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
 196    ldr   sp, =__stack_irq_end
 197
 198    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
 199    ldr   sp, =__stack_svc_end
 200
 201
 202    /*
 203     * Clear .bss section
 204     */
 205    ldr   r1, =__bss_start
 206    ldr   r2, =__bss_end
 207    ldr   r3, =0
 208 bss_clear_loop:
 209    cmp   r1, r2
 210    strne r3, [r1], #+4
 211    bne   bss_clear_loop
 212
 213
 214    /*
 215     * Jump to main
 216     */
 217    mrs   r0, cpsr
 218    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
 219    msr   cpsr, r0
 220
 221    mov   r0, #0 /* No arguments */
 222    mov   r1, #0 /* No arguments */
 223    ldr   r2, =main
 224    mov   lr, pc
 225    bx    r2     /* And jump... */
 226
 227 ExitFunction:
 228    nop
 229    nop
 230    nop
 231    b ExitFunction
 232
 233
 234 /****************************************************************************/
 235 /*                         Default interrupt handler                        */
 236 /****************************************************************************/
 237
 238 UndefHandler:
 239    b UndefHandler
 240
 241 SWIHandler:
 242    b SWIHandler
 243
 244 PAbortHandler:
 245    b PAbortHandler
 246
 247 DAbortHandler:
 248    b DAbortHandler
 249
 250 IRQHandler:
 251    b IRQHandler
 252
 253 FIQHandler:
 254    b FIQHandler
 255
 256    .weak ExitFunction
 257    .weak UndefHandler, PAbortHandler, DAbortHandler
 258    .weak IRQHandler, FIQHandler
 259
 260    .ltorg
 261 /*** EOF ***/