tcl/target/stm32h7x.cfg

   1 # script for stm32h7x family
   2
   3 #
   4 # stm32h7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32h7x
  13 }
  14
  15 if { [info exists DUAL_BANK] } {
  16         set $_CHIPNAME.DUAL_BANK $DUAL_BANK
  17         unset DUAL_BANK
  18 } else {
  19         set $_CHIPNAME.DUAL_BANK 0
  20 }
  21
  22 if { [info exists DUAL_CORE] } {
  23         set $_CHIPNAME.DUAL_CORE $DUAL_CORE
  24         unset DUAL_CORE
  25 } else {
  26         set $_CHIPNAME.DUAL_CORE 0
  27 }
  28
  29 # Issue a warning when hla is used, and fallback to single core configuration
  30 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
  31         echo "Warning : hla does not support multicore debugging"
  32         set $_CHIPNAME.DUAL_CORE 0
  33 }
  34
  35 if { [info exists USE_CTI] } {
  36         set $_CHIPNAME.USE_CTI $USE_CTI
  37         unset USE_CTI
  38 } else {
  39         set $_CHIPNAME.USE_CTI 0
  40 }
  41
  42 # Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
  43 if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
  44         echo "Warning : could not use CTI with a single core device, CTI is disabled"
  45         set $_CHIPNAME.USE_CTI 0
  46 }
  47
  48 set _ENDIAN little
  49
  50 # Work-area is a space in RAM used for flash programming
  51 # By default use 64kB
  52 if { [info exists WORKAREASIZE] } {
  53    set _WORKAREASIZE $WORKAREASIZE
  54 } else {
  55    set _WORKAREASIZE 0x10000
  56 }
  57
  58 #jtag scan chain
  59 if { [info exists CPUTAPID] } {
  60    set _CPUTAPID $CPUTAPID
  61 } else {
  62    if { [using_jtag] } {
  63           set _CPUTAPID 0x6ba00477
  64    } {
  65       set _CPUTAPID 0x6ba02477
  66    }
  67 }
  68
  69 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  70 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  71
  72 if {[using_jtag]} {
  73    jtag newtap $_CHIPNAME bs -irlen 5
  74 }
  75
  76 if {![using_hla]} {
  77         # STM32H7 provides an APB-AP at access port 2, which allows the access to
  78         # the debug and trace features on the system APB System Debug Bus (APB-D).
  79         target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
  80         swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
  81         tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
  82 }
  83
  84 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
  85
  86 $_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  87
  88 flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
  89
  90 if {[set $_CHIPNAME.DUAL_BANK]} {
  91         flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
  92 }
  93
  94 if {[set $_CHIPNAME.DUAL_CORE]} {
  95         target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
  96
  97         $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  98
  99         flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
 100
 101         if {[set $_CHIPNAME.DUAL_BANK]} {
 102                 flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
 103         }
 104 }
 105
 106 # Make sure that cpu0 is selected
 107 targets $_CHIPNAME.cpu0
 108
 109 if { [info exists QUADSPI] && $QUADSPI } {
 110    set a [llength [flash list]]
 111    set _QSPINAME $_CHIPNAME.qspi
 112    flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
 113 } else {
 114    if { [info exists OCTOSPI1] && $OCTOSPI1 } {
 115       set a [llength [flash list]]
 116       set _OCTOSPINAME1 $_CHIPNAME.octospi1
 117       flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
 118    }
 119    if { [info exists OCTOSPI2] && $OCTOSPI2 } {
 120       set b [llength [flash list]]
 121       set _OCTOSPINAME2 $_CHIPNAME.octospi2
 122       flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
 123    }
 124 }
 125
 126 # Clock after reset is HSI at 64 MHz, no need of PLL
 127 adapter speed 1800
 128
 129 adapter srst delay 100
 130 if {[using_jtag]} {
 131  jtag_ntrst_delay 100
 132 }
 133
 134 # use hardware reset
 135 #
 136 # The STM32H7 does not support connect_assert_srst mode because the AXI is
 137 # unavailable while SRST is asserted, and that is used to access the DBGMCU
 138 # component at 0x5C001000 in the examine-end event handler.
 139 #
 140 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
 141 # of the default AP0, and that works with SRST asserted; however, nonzero AP
 142 # usage does not work with HLA, so is not done by default. That change could be
 143 # made in a local configuration file if connect_assert_srst mode is needed for
 144 # a specific application and a non-HLA adapter is in use.
 145 reset_config srst_only srst_nogate
 146
 147 if {![using_hla]} {
 148    # if srst is not fitted use SYSRESETREQ to
 149    # perform a soft reset
 150         $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
 151
 152         if {[set $_CHIPNAME.DUAL_CORE]} {
 153                 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
 154         }
 155
 156    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
 157    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
 158    # makes the data access cacheable. This allows reading and writing data in the
 159    # CPU cache from the debugger, which is far more useful than going straight to
 160    # RAM when operating on typical variables, and is generally no worse when
 161    # operating on special memory locations.
 162    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 163 }
 164
 165 $_CHIPNAME.cpu0 configure -event examine-end {
 166         # Enable D3 and D1 DBG clocks
 167         # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
 168         stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 169
 170         # Enable debug during low power modes (uses more power)
 171         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
 172         stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
 173         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
 174         stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
 175
 176         # Stop watchdog counters during halt
 177         # DBGMCU_APB3FZ1 |= WWDG1
 178         stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
 179         # DBGMCU_APB1LFZ1 |= WWDG2
 180         stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
 181         # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
 182         stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
 183
 184         # Enable clock for tracing
 185         # DBGMCU_CR |= TRACECLKEN
 186         stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 187
 188         # RM0399 (id 0x450) M7+M4 with SWO Funnel
 189         # RM0433 (id 0x450) M7 with SWO Funnel
 190         # RM0455 (id 0x480) M7 without SWO Funnel
 191         # RM0468 (id 0x483) M7 without SWO Funnel
 192         # Enable CM7 and CM4 slave ports in SWO trace Funnel
 193         # Works ok also on devices single core and without SWO funnel
 194         # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
 195         # SWTF_CTRL |= ENS0 | ENS1
 196         stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
 197 }
 198
 199 $_CHIPNAME.cpu0 configure -event reset-init {
 200         # Clock after reset is HSI at 64 MHz, no need of PLL
 201         adapter speed 4000
 202 }
 203
 204 # get _CHIPNAME from current target
 205 proc stm32h7x_get_chipname {} {
 206         set t [target current]
 207         set sep [string last "." $t]
 208         if {$sep == -1} {
 209                 return $t
 210         }
 211         return [string range $t 0 [expr {$sep - 1}]]
 212 }
 213
 214 if {[set $_CHIPNAME.DUAL_CORE]} {
 215         $_CHIPNAME.cpu1 configure -event examine-end {
 216                 set _CHIPNAME [stm32h7x_get_chipname]
 217                 global $_CHIPNAME.USE_CTI
 218
 219                 # Stop watchdog counters during halt
 220                 # DBGMCU_APB3FZ2 |= WWDG1
 221                 stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
 222                 # DBGMCU_APB1LFZ2 |= WWDG2
 223                 stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
 224                 # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
 225                 stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
 226
 227                 if {[set $_CHIPNAME.USE_CTI]} {
 228                         stm32h7x_cti_start
 229                 }
 230         }
 231 }
 232
 233 # like mrw, but with target selection
 234 proc stm32h7x_mrw {used_target reg} {
 235         set value ""
 236         $used_target mem2array value 32 $reg 1
 237         return $value(0)
 238 }
 239
 240 # like mmw, but with target selection
 241 proc stm32h7x_mmw {used_target reg setbits clearbits} {
 242         set old [stm32h7x_mrw $used_target $reg]
 243         set new [expr {($old & ~$clearbits) | $setbits}]
 244         $used_target mww $reg $new
 245 }
 246
 247 # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
 248 # this procedure will use the mem_ap on AP2 whenever possible
 249 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 250         # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
 251         if {![using_hla]} {
 252                 set _CHIPNAME [stm32h7x_get_chipname]
 253                 set used_target $_CHIPNAME.ap2
 254                 set reg_addr [expr {0xE00E1000 + $reg_offset}]
 255         } {
 256                 set used_target [target current]
 257                 set reg_addr [expr {0x5C001000 + $reg_offset}]
 258         }
 259
 260         stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 261 }
 262
 263 if {[set $_CHIPNAME.USE_CTI]} {
 264         # create CTI instances for both cores
 265         cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
 266         cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
 267
 268         $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
 269         $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
 270
 271         $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
 272         $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
 273
 274         proc stm32h7x_cti_start {} {
 275                 set _CHIPNAME [stm32h7x_get_chipname]
 276
 277                 # Configure Cores' CTIs to halt each other
 278                 # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
 279                 $_CHIPNAME.cti0 write INEN0 0x1
 280                 $_CHIPNAME.cti0 write OUTEN0 0x1
 281                 $_CHIPNAME.cti1 write INEN0 0x1
 282                 $_CHIPNAME.cti1 write OUTEN0 0x1
 283
 284                 # enable CTIs
 285                 $_CHIPNAME.cti0 enable on
 286                 $_CHIPNAME.cti1 enable on
 287         }
 288
 289         proc stm32h7x_cti_stop {} {
 290                 set _CHIPNAME [stm32h7x_get_chipname]
 291
 292                 $_CHIPNAME.cti0 enable off
 293                 $_CHIPNAME.cti1 enable off
 294         }
 295
 296         proc stm32h7x_cti_prepare_restart_all {} {
 297                 stm32h7x_cti_prepare_restart cti0
 298                 stm32h7x_cti_prepare_restart cti1
 299         }
 300
 301         proc stm32h7x_cti_prepare_restart {cti} {
 302                 set _CHIPNAME [stm32h7x_get_chipname]
 303
 304                 # Acknowlodge EDBGRQ at TRIGOUT0
 305                 $_CHIPNAME.$cti write INACK 0x01
 306                 $_CHIPNAME.$cti write INACK 0x00
 307         }
 308 }