tcl/target/stellaris.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # TI/Luminary Stellaris LM3S chip family
   4
   5 # Some devices have errata in returning their device class.
   6 # DEVICECLASS is provided as a manual override
   7 # Manual setting of a device class of 0xff is not allowed
   8
   9 global _DEVICECLASS
  10
  11 if { [info exists DEVICECLASS] } {
  12    set _DEVICECLASS $DEVICECLASS
  13 } else {
  14    set _DEVICECLASS 0xff
  15 }
  16
  17 # Luminary chips support both JTAG and SWD transports.
  18 # Adapt based on what transport is active.
  19 source [find target/swj-dp.tcl]
  20
  21 # For now we ignore the SPI and UART options, which
  22 # are usable only for ISP style initial flash programming.
  23
  24 if { [info exists CHIPNAME] } {
  25    set _CHIPNAME $CHIPNAME
  26 } else {
  27    set _CHIPNAME lm3s
  28 }
  29
  30 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  31 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  32 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  33 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
  34 # CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
  35 # ... we'll ignore the JTAG version field, rather than list every
  36 # chip revision that turns up.
  37 if { [info exists CPUTAPID] } {
  38    set _CPUTAPID $CPUTAPID
  39 } else {
  40    set _CPUTAPID 0x0ba00477
  41 }
  42
  43 # SWD DAP, and JTAG TAP, take same params for now;
  44 # ... even though SWD ignores all except TAPID, and
  45 # JTAG shouldn't need anything more then irlen. (and TAPID).
  46 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  47     -expected-id $_CPUTAPID -ignore-version
  48 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  49
  50 if { [info exists WORKAREASIZE] } {
  51    set _WORKAREASIZE $WORKAREASIZE
  52 } else {
  53    # default to 2K working area
  54    set _WORKAREASIZE 0x800
  55 }
  56
  57 set _TARGETNAME $_CHIPNAME.cpu
  58 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  59
  60 # 8K working area at base of ram, not backed up
  61 #
  62 # NOTE: you may need or want to reconfigure the work area;
  63 # some parts have just 6K, and you may want to use other
  64 # addresses (at end of mem not beginning) or back it up.
  65 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  66
  67 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  68 # LM3S parts don't support RTCK
  69 #
  70 # NOTE: this may be increased by a reset-init handler, after it
  71 # configures and enables the PLL.  Or you might need to decrease
  72 # this, if you're using a slower clock.
  73 adapter speed 500
  74
  75 source [find mem_helper.tcl]
  76
  77 proc reset_peripherals {family} {
  78
  79         source [find chip/ti/lm3s/lm3s.tcl]
  80
  81         echo "Resetting Core Peripherals"
  82
  83         # Disable the PLL and the system clock divider (nop if disabled)
  84         mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
  85         mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
  86
  87         # RCC and RCC2 to their reset values
  88         mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
  89         mww $SYSCTL_RCC2 0x07806810
  90         mww $SYSCTL_RCC 0x078e3ad1
  91
  92         # Reset the deep sleep clock configuration register
  93         mww $SYSCTL_DSLPCLKCFG 0x07800000
  94
  95         # Reset the clock gating registers
  96         mww $SYSCTL_RCGC0 0x00000040
  97         mww $SYSCTL_RCGC1 0
  98         mww $SYSCTL_RCGC2 0
  99         mww $SYSCTL_SCGC0 0x00000040
 100         mww $SYSCTL_SCGC1 0
 101         mww $SYSCTL_SCGC2 0
 102         mww $SYSCTL_DCGC0 0x00000040
 103         mww $SYSCTL_DCGC1 0
 104         mww $SYSCTL_DCGC2 0
 105
 106         # Reset the remaining SysCtl registers
 107         mww $SYSCTL_PBORCTL 0
 108         mww $SYSCTL_IMC 0
 109         mww $SYSCTL_GPIOHBCTL 0
 110         mww $SYSCTL_MOSCCTL 0
 111         mww $SYSCTL_PIOSCCAL 0
 112         mww $SYSCTL_I2SMCLKCFG 0
 113
 114         # Reset the peripherals
 115         mww $SYSCTL_SRCR0 0xffffffff
 116         mww $SYSCTL_SRCR1 0xffffffff
 117         mww $SYSCTL_SRCR2 0xffffffff
 118         mww $SYSCTL_SRCR0 0
 119         mww $SYSCTL_SRCR1 0
 120         mww $SYSCTL_SRCR2 0
 121
 122         # Clear any pending SysCtl interrupts
 123         mww $SYSCTL_MISC 0xffffffff
 124
 125         # Wait for any pending flash operations to complete
 126         while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
 127         while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
 128
 129         # Reset the flash controller registers
 130         mww $FLASH_FMA 0
 131         mww $FLASH_FCIM 0
 132         mww $FLASH_FCMISC 0xffffffff
 133         mww $FLASH_FWBVAL 0
 134 }
 135
 136 $_TARGETNAME configure -event reset-start {
 137         adapter speed 500
 138
 139         #
 140         # When nRST is asserted on most Stellaris devices, it clears some of
 141         # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 142         # and OpenOCD depends on those TRMs.  So we won't use SRST on those
 143         # chips.  (Only power-on reset should affect debug state, beyond a
 144         # few specified bits; not the chip's nRST input, wired to SRST.)
 145         #
 146         # REVISIT current errata specs don't seem to cover this issue.
 147         # Do we have more details than this email?
 148         #   https://lists.berlios.de/pipermail
 149         #       /openocd-development/2008-August/003065.html
 150         #
 151
 152         global _DEVICECLASS
 153
 154         if {$_DEVICECLASS != 0xff} {
 155            set device_class $_DEVICECLASS
 156         } else {
 157            set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
 158         }
 159
 160         if {$device_class == 0 || $device_class == 1 ||
 161                 $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
 162                 if {![using_hla]} {
 163                    # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
 164                    cortex_m reset_config sysresetreq
 165                 }
 166         } else {
 167                 if {![using_hla]} {
 168                    # Tempest and Firestorm default to using NVIC VECTRESET
 169                    # peripherals will need resetting manually, see proc reset_peripherals
 170                    cortex_m reset_config vectreset
 171                 }
 172                 # reset peripherals, based on code in
 173                 # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
 174                 reset_peripherals $device_class
 175         }
 176 }
 177
 178 # flash configuration ... autodetects sizes, autoprobed
 179 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME