tcl/target/psoc6.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
   5 # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
   6 # the same Flash/RAM/MMIO address space.
   7 #
   8
   9 source [find target/swj-dp.tcl]
  10
  11 adapter speed 1000
  12
  13 global _CHIPNAME
  14 if { [info exists CHIPNAME] } {
  15         set _CHIPNAME $CHIPNAME
  16 } else {
  17         set _CHIPNAME psoc6
  18 }
  19
  20 global TARGET
  21 set TARGET $_CHIPNAME.cpu
  22
  23 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
  24 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  25
  26 # Is CM0 Debugging enabled ?
  27 global _ENABLE_CM0
  28 if { [info exists ENABLE_CM0] } {
  29         set _ENABLE_CM0 $ENABLE_CM0
  30 } else {
  31         set _ENABLE_CM0 1
  32 }
  33
  34 # Is CM4 Debugging enabled ?
  35 global _ENABLE_CM4
  36 if { [info exists ENABLE_CM4] } {
  37         set _ENABLE_CM4 $ENABLE_CM4
  38 } else {
  39         set _ENABLE_CM4 1
  40 }
  41
  42 global _WORKAREASIZE_CM0
  43 if { [info exists WORKAREASIZE_CM0] } {
  44         set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
  45 } else {
  46         set _WORKAREASIZE_CM0 0x4000
  47 }
  48
  49 global _WORKAREASIZE_CM4
  50 if { [info exists WORKAREASIZE_CM4] } {
  51         set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
  52 } else {
  53         set _WORKAREASIZE_CM4 0x4000
  54 }
  55
  56 global _WORKAREAADDR_CM0
  57 if { [info exists WORKAREAADDR_CM0] } {
  58         set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
  59 } else {
  60         set _WORKAREAADDR_CM0 0x08000000
  61 }
  62
  63 global _WORKAREAADDR_CM4
  64 if { [info exists WORKAREAADDR_CM4] } {
  65         set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
  66 } else {
  67         set _WORKAREAADDR_CM4 0x08000000
  68 }
  69
  70 proc init_reset { mode } {
  71         global RESET_MODE
  72         set RESET_MODE $mode
  73
  74         if {[using_jtag]} {
  75                 jtag arp_init-reset
  76         }
  77 }
  78
  79 # Utility to make 'reset halt' work as reset;halt on a target
  80 # It does not prevent running code after reset
  81 proc psoc6_deassert_post { target } {
  82         # PSoC6 cleared AP registers including TAR during reset
  83         # Force examine to synchronize OpenOCD target status
  84         $target arp_examine
  85
  86         global RESET_MODE
  87         global TARGET
  88
  89         if { $RESET_MODE ne "run" } {
  90                 $target arp_poll
  91                 $target arp_poll
  92                 set st [$target curstate]
  93
  94                 if { $st eq "reset" } {
  95                         # we assume running state follows
  96                         # if reset accidentally halts, waiting is useless
  97                         catch { $target arp_waitstate running 100 }
  98                         set st [$target curstate]
  99                 }
 100
 101                 if { $st eq "running" } {
 102                         echo "$target: Ran after reset and before halt..."
 103                         if { $target eq "${TARGET}.cm0" } {
 104                                 # Try to cleanly reset whole system
 105                                 # and halt the CM0 at entry point
 106                                 psoc6 reset_halt
 107                                 $target arp_waitstate halted 100
 108                         } else {
 109                                 $target arp_halt
 110                         }
 111                 }
 112         }
 113 }
 114
 115 if { $_ENABLE_CM0 } {
 116         target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
 117         ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
 118
 119         flash bank main_flash_cm0               psoc6 0x10000000 0 0 0 ${TARGET}.cm0
 120         flash bank work_flash_cm0               psoc6 0x14000000 0 0 0 ${TARGET}.cm0
 121         flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
 122         flash bank super_flash_nar_cm0  psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
 123         flash bank super_flash_key_cm0  psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
 124         flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
 125
 126         ${TARGET}.cm0 cortex_m reset_config sysresetreq
 127         ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
 128 }
 129
 130 if { $_ENABLE_CM4 } {
 131         target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
 132         ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
 133
 134         flash bank main_flash_cm4               psoc6 0x10000000 0 0 0 ${TARGET}.cm4
 135         flash bank work_flash_cm4               psoc6 0x14000000 0 0 0 ${TARGET}.cm4
 136         flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
 137         flash bank super_flash_nar_cm4  psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
 138         flash bank super_flash_key_cm4  psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
 139         flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
 140
 141         ${TARGET}.cm4 cortex_m reset_config vectreset
 142         ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
 143 }
 144
 145 if { $_ENABLE_CM0 } {
 146         # Use CM0+ by default on dual-core devices
 147         targets ${TARGET}.cm0
 148 }
 149
 150 if {[using_jtag]} {
 151         jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
 152 }