tcl/target/marvell/cn9130.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
   4 #
   5 # henrik.nordstorm@addiva.se, Nov 2023
   6
   7 if { [info exists CHIPNAME] } {
   8    set _CHIPNAME $CHIPNAME
   9 } else {
  10    set _CHIPNAME cn9130
  11 }
  12
  13 if { [info exists MASTERTAPID] } {
  14    set _MASTERTAPID $MASTERTAPID
  15 } else {
  16    set _MASTERTAPID 0x07025357
  17 }
  18
  19 if { [info exists APTAPID] } {
  20    set _APTAPID $APTAPID
  21 } else {
  22    set _APTAPID 0x4ba00477
  23 }
  24
  25 if { [info exists SBTAPID] } {
  26    set _SBTAPID $SBTAPID
  27 } else {
  28    set _SBTAPID 0x4ba00477
  29 }
  30
  31 if { [info exists CORES] } {
  32    set _CORES $CORES
  33 } else {
  34    set _CORES 4
  35 }
  36
  37 # CTI base address should be possible to read from the CoreSight
  38 # ROM table like how the DBG base address is when not specified.
  39 if { [info exists CTIBASE] } {
  40    set _CTIBASE $CTIBASE
  41 } else {
  42    set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  43 }
  44
  45 # CN9130 is a multi-die chip and has a multi level hierarchical
  46 # JTAG TAP, where all the DAPs are disabled at reset, requiring
  47 # both configuration to enable access to the chip DAPs, and a
  48 # vendor specific bypass IR instruction to access the slave TAPs
  49 # via the master TAP. In addition there is a number of sample
  50 # bits that should be ignored.
  51 #
  52 # The default BYPASS instruction in the master TAP bypasses the
  53 # whole chip and not only the master TAP. And similarly on
  54 # IDCODE the master TAP only responds with it's own ID and
  55 # bypasses the other TAPs on the chip, while OpenOCD expects
  56 # ID from all enabled TAPs in the chain.
  57
  58 # Bootstrap with the default boundary scan oriented TAP configuration
  59 # where the master,ap,sb TAPs are seen as one big fat TAP, which matches
  60 # what OpenOCD expects from IDCODE and BYPASS.
  61
  62 jtag newtap $_CHIPNAME bs  -irlen 19 -enable -expected-id $_MASTERTAPID
  63
  64 # Declare the full JTAG chain, but in disabled state during setup
  65
  66 jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
  67 jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
  68 jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
  69 jtag newtap $_CHIPNAME ap.cpu  -irlen 4 -disable -expected-id $_APTAPID
  70 jtag newtap $_CHIPNAME ap      -irlen 5 -disable
  71 jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
  72 jtag newtap $_CHIPNAME sb.cpu  -irlen 4 -disable -expected-id $_SBTAPID
  73 jtag newtap $_CHIPNAME sb      -irlen 5 -disable
  74 jtag newtap $_CHIPNAME master  -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
  75
  76 # Once the iniial IDCODE scan has completed switch to more detailed
  77 # scan chain giving access to the individual chip TAPs.
  78
  79 jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
  80
  81 proc cn9130_enable_full_chain { _CHIPNAME } {
  82    # Switch to detailed TAP declaration
  83    jtag tapdisable $_CHIPNAME.bs
  84    jtag tapenable $_CHIPNAME.master
  85    jtag tapenable $_CHIPNAME.sb
  86    jtag tapenable $_CHIPNAME.sample1
  87    jtag tapenable $_CHIPNAME.ap
  88    jtag tapenable $_CHIPNAME.sample2
  89    jtag tapenable $_CHIPNAME.sample3
  90    jtag tapenable $_CHIPNAME.sample4
  91 }
  92
  93 # AP & SB TAPs have a config register to enable/disable access to
  94 # the auxilary DAP TAP. Default off which hides the DAP TAP from
  95 # the scan chain.
  96 proc cn9130_dap_config { chip tap state } {
  97    irscan $chip.$tap 0x12
  98    drscan $chip.$tap 32 $state
  99 }
 100
 101 jtag configure $_CHIPNAME.bs -event tap-disable ""
 102 jtag configure $_CHIPNAME.bs -event tap-enable ""
 103 jtag configure $_CHIPNAME.sample4 -event tap-enable ""
 104 jtag configure $_CHIPNAME.sample3 -event tap-enable ""
 105 jtag configure $_CHIPNAME.sample2 -event tap-enable ""
 106 jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
 107 jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
 108 jtag configure $_CHIPNAME.ap -event tap-enable ""
 109 jtag configure $_CHIPNAME.sample1 -event tap-enable ""
 110 jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
 111 jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
 112 jtag configure $_CHIPNAME.sb -event tap-enable ""
 113 jtag configure $_CHIPNAME.master -event tap-enable ""
 114
 115 dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
 116
 117 # Main bus
 118 target create $_CHIPNAME.ap.axi mem_ap \
 119    -dap $_CHIPNAME.ap.dap \
 120    -ap-num 0
 121
 122 # Periperials bus
 123 target create $_CHIPNAME.ap.apb mem_ap \
 124    -dap $_CHIPNAME.ap.dap \
 125    -ap-num 1
 126
 127 # MSS bus
 128 target create $_CHIPNAME.ap.ahb mem_ap \
 129    -dap $_CHIPNAME.ap.dap \
 130    -ap-num 2
 131
 132 # AP A72 CPU cores
 133 set _smp_command ""
 134 for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
 135    cti create $_CHIPNAME.ap.cti.$_core \
 136       -dap $_CHIPNAME.ap.dap \
 137       -baseaddr [ lindex $_CTIBASE $_core ]  \
 138       -ap-num 1
 139
 140    if { $_core == 0 } {
 141       target create $_CHIPNAME.ap.a72.$_core aarch64 \
 142          -dap $_CHIPNAME.ap.dap \
 143          -ap-num 1 \
 144          -cti $_CHIPNAME.ap.cti.$_core \
 145          -coreid $_core \
 146          -rtos hwthread
 147       set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
 148    } else {
 149       # Defer non-boot cores. Held hard in reset until
 150       # SMP is activated.
 151       target create $_CHIPNAME.ap.a72.$_core aarch64 \
 152          -dap $_CHIPNAME.ap.dap \
 153          -ap-num 1 \
 154          -cti $_CHIPNAME.ap.cti.$_core \
 155          -coreid $_core \
 156          -defer-examine
 157       set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
 158    }
 159
 160 }
 161
 162 # Set up the A72 cluster as SMP
 163 # Note: Only the boot core is active by default. The other core DAPs can
 164 # be enabled by arp_examine after they have been released from hard reset.
 165 eval $_smp_command
 166
 167 # AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
 168 target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
 169
 170 # Why is this needed? reset fails with "Debug regions are unpowered" otherwise
 171 $_CHIPNAME.ap.axi configure -event examine-start "dap init"
 172
 173 # Automate enabling the AP A72 DAP once the full scan chain is enabled
 174 proc cn9130_ap_setup { _CHIPNAME } {
 175    jtag tapenable $_CHIPNAME.ap.cpu
 176    targets $_CHIPNAME.ap.a72.0
 177 }
 178 jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"