jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / tcl / target / atsamv.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2
3 # ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
4 # The chips are very similar; the SAMV series just has
5 # more peripherals and seems like the "flagship" of the
6 # family. This script will work for all of them.
7
8 source [find target/swj-dp.tcl]
9
10 if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
12 } else {
13 set _CHIPNAME samv
14 }
15
16 if { [info exists ENDIAN] } {
17 set _ENDIAN $ENDIAN
18 } else {
19 set _ENDIAN little
20 }
21
22 # Work-area is a space in RAM used for flash programming
23 # By default use 16kB
24 if { [info exists WORKAREASIZE] } {
25 set _WORKAREASIZE $WORKAREASIZE
26 } else {
27 set _WORKAREASIZE 0x4000
28 }
29
30 if { [info exists CPUTAPID] } {
31 set _CPUTAPID $CPUTAPID
32 } else {
33 set _CPUTAPID 0x0bd11477
34 }
35
36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
38
39 set _TARGETNAME $_CHIPNAME.cpu
40 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
41
42 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
43
44 adapter speed 1800
45
46 if {![using_hla]} {
47 # if srst is not fitted use SYSRESETREQ to
48 # perform a soft reset
49 cortex_m reset_config sysresetreq
50
51 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
52 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
53 # makes the data access cacheable. This allows reading and writing data in the
54 # CPU cache from the debugger, which is far more useful than going straight to
55 # RAM when operating on typical variables, and is generally no worse when
56 # operating on special memory locations.
57 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
58 }
59
60 set _FLASHNAME $_CHIPNAME.flash
61 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME

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