tcl/board/tp-link_wdr4300.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 source [find target/atheros_ar9344.cfg]
   4
   5 reset_config trst_only separate
   6
   7 proc ar9344_40mhz_pll_init {} {
   8         # QCA_PLL_SRIF_CPU_DPLL2_REG
   9         mww 0xb81161C4 0x13210f00
  10         # QCA_PLL_SRIF_CPU_DPLL3_REG
  11         mww 0xb81161C8 0x03000000
  12         # QCA_PLL_SRIF_DDR_DPLL2_REG
  13         mww 0xb8116244 0x13210f00
  14         # QCA_PLL_SRIF_DDR_DPLL3_REG
  15         mww 0xb8116248 0x03000000
  16         # QCA_PLL_SRIF_BB_DPLL_BASE_REG
  17         mww 0xb8116188 0x03000000
  18
  19         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
  20         mww 0xb8050008 0x0130001C
  21         mww 0xb8050008 0x0130001C
  22         mww 0xb8050008 0x0130001C
  23
  24         # QCA_PLL_CPU_PLL_CFG_REG
  25         mww 0xb8050000 0x40021380
  26         # QCA_PLL_DDR_PLL_CFG_REG
  27         mww 0xb8050004 0x40815800
  28         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
  29         mww 0xb8050008 0x0130801C
  30
  31         # QCA_PLL_SRIF_CPU_DPLL2_REG
  32         mww 0xb81161C4 0x10810F00
  33         mww 0xb81161C0 0x41C00000
  34         # QCA_PLL_SRIF_CPU_DPLL2_REG
  35         mww 0xb81161C4 0xD0810F00
  36         # QCA_PLL_SRIF_CPU_DPLL3_REG
  37         mww 0xb81161C8 0x03000000
  38         # QCA_PLL_SRIF_CPU_DPLL2_REG
  39         mww 0xb81161C4 0xD0800F00
  40
  41         # QCA_PLL_SRIF_CPU_DPLL3_REG
  42         mww 0xb81161C8 0x03000000
  43         # QCA_PLL_SRIF_CPU_DPLL3_REG
  44         mww 0xb81161C8 0x43000000
  45         # QCA_PLL_SRIF_CPU_DPLL3_REG
  46         mww 0xb81161C8 0x030003E8
  47
  48         # QCA_PLL_SRIF_DDR_DPLL2_REG
  49         mww 0xb8116244 0x10810F00
  50         mww 0xb8116240 0x41680000
  51         # QCA_PLL_SRIF_DDR_DPLL2_REG
  52         mww 0xb8116244 0xD0810F00
  53         # QCA_PLL_SRIF_DDR_DPLL3_REG
  54         mww 0xb8116248 0x03000000
  55         # QCA_PLL_SRIF_DDR_DPLL2_REG
  56         mww 0xb8116244 0xD0800F00
  57
  58         # QCA_PLL_SRIF_DDR_DPLL3_REG
  59         mww 0xb8116248 0x03000000
  60         # QCA_PLL_SRIF_DDR_DPLL3_REG
  61         mww 0xb8116248 0x43000000
  62         # QCA_PLL_SRIF_DDR_DPLL3_REG
  63         mww 0xb8116248 0x03000718
  64
  65         # QCA_PLL_CPU_DDR_CLK_CTRL_REG
  66         mww 0xb8050008 0x01308018
  67         mww 0xb8050008 0x01308010
  68         mww 0xb8050008 0x01308000
  69
  70         # QCA_PLL_DDR_PLL_DITHER_REG
  71         mww 0xb8050044 0x78180200
  72         # QCA_PLL_CPU_PLL_DITHER_REG
  73         mww 0xb8050048 0x41C00000
  74
  75 }
  76
  77 proc ar9344_ddr_init {} {
  78         # QCA_DDR_CTRL_CFG_REG
  79         mww 0xb8000108 0x40
  80         # QCA_DDR_RD_DATA_THIS_CYCLE_REG
  81         mww 0xb8000018 0xFF
  82         # QCA_DDR_BURST_REG
  83         mww 0xb80000C4 0x74444444
  84         # QCA_DDR_BURST2_REG
  85         mww 0xb80000C8 0x0222
  86         # QCA_AHB_MASTER_TOUT_MAX_REG
  87         mww 0xb80000CC 0xFFFFF
  88
  89         # QCA_DDR_CFG_REG
  90         mww 0xb8000000 0xC7D48CD0
  91         # QCA_DDR_CFG2_REG
  92         mww 0xb8000004 0x9DD0E6A8
  93
  94         # QCA_DDR_DDR2_CFG_REG
  95         mww 0xb80000B8 0x0E59
  96         # QCA_DDR_CFG2_REG
  97         mww 0xb8000004 0x9DD0E6A8
  98
  99         # QCA_DDR_CTRL_REG
 100         mww 0xb8000010 0x08
 101         mww 0xb8000010 0x08
 102         mww 0xb8000010 0x10
 103         mww 0xb8000010 0x20
 104         # QCA_DDR_EMR_REG
 105         mww 0xb800000C 0x02
 106         # QCA_DDR_CTRL_REG
 107         mww 0xb8000010 0x02
 108
 109         # QCA_DDR_MR_REG
 110         mww 0xb8000008 0x0133
 111         # QCA_DDR_CTRL_REG
 112         mww 0xb8000010 0x1
 113         mww 0xb8000010 0x8
 114         mww 0xb8000010 0x8
 115         mww 0xb8000010 0x4
 116         mww 0xb8000010 0x4
 117
 118         # QCA_DDR_MR_REG
 119         mww 0xb8000008 0x33
 120         # QCA_DDR_CTRL_REG
 121         mww 0xb8000010 0x1
 122
 123         # QCA_DDR_EMR_REG
 124         mww 0xb800000C 0x0382
 125         # QCA_DDR_CTRL_REG
 126         mww 0xb8000010 0x2
 127         # QCA_DDR_EMR_REG
 128         mww 0xb800000C 0x0402
 129         # QCA_DDR_CTRL_REG
 130         mww 0xb8000010 0x2
 131
 132         # QCA_DDR_REFRESH_REG
 133         mww 0xb8000014 0x4270
 134
 135         # QCA_DDR_TAP_CTRL_0_REG
 136         mww 0xb800001C 0x0e
 137         # QCA_DDR_TAP_CTRL_1_REG
 138         mww 0xb8000020 0x0e
 139         # QCA_DDR_TAP_CTRL_2_REG
 140         mww 0xb8000024 0x0e
 141         # QCA_DDR_TAP_CTRL_3_REG
 142         mww 0xb8000028 0x0e
 143 }
 144
 145 $_TARGETNAME configure -event reset-init {
 146
 147         # mww 0xb806001c 0x1000000
 148         ar9344_40mhz_pll_init
 149         sleep 100
 150
 151         # flash remap
 152         # SPI_CONTROL_ADDR
 153         mww 0xbF000004 0x43
 154
 155         ar9344_ddr_init
 156         sleep 100
 157 }
 158
 159 set ram_boot_address 0xa0000000
 160 $_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
 161
 162 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0