tcl/board/stm32f412g-disco.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
   4 # http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
   5
   6 # This is for using the onboard STLINK
   7 source [find interface/stlink.cfg]
   8
   9 transport select hla_swd
  10
  11 # increase working area to 128KB
  12 set WORKAREASIZE 0x20000
  13
  14 # enable stmqspi
  15 set QUADSPI 1
  16
  17 source [find target/stm32f4x.cfg]
  18
  19 # QUADSPI initialization
  20 proc qspi_init { } {
  21         global a
  22         mmw 0x40023830 0x000000FF 0                             ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
  23         mmw 0x40023838 0x00000002 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  24         sleep 1                                                                 ;# Wait for clock startup
  25
  26         # PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
  27
  28         # PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
  29
  30         # Port B: PB02:AF09:V
  31         mmw 0x40020400 0x00000020 0x00000010    ;# MODER
  32         mmw 0x40020408 0x00000030 0x00000000    ;# OSPEEDR
  33         mmw 0x40020420 0x00000900 0x00000600    ;# AFRL
  34
  35         # Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
  36         mmw 0x40021400 0x000AA000 0x00055000    ;# MODER
  37         mmw 0x40021408 0x000FF000 0x00000000    ;# OSPEEDR
  38         mmw 0x40021420 0x99000000 0x66000000    ;# AFRL
  39         mmw 0x40021424 0x000000AA 0x00000055    ;# AFRH
  40
  41         # Port G: PG06:AF10:V
  42         mmw 0x40021800 0x00002000 0x00001000    ;# MODER
  43         mmw 0x40021808 0x00003000 0x00000000    ;# OSPEEDR
  44         mmw 0x40021820 0x0A000000 0x05000000    ;# AFRL
  45
  46         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  47         mww 0xA0001000 0x03500008                               ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  48         mww 0xA0001004 0x00170100                               ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
  49         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  50
  51         # 1-line spi mode
  52         mww 0xA0001014 0x000003F5                               ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
  53         sleep 1
  54
  55         # memory-mapped read mode with 3-byte addresses
  56         mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
  57 }
  58
  59 $_TARGETNAME configure -event reset-init {
  60         mww 0x40023C00 0x00000003                               ;# 3 WS for 96 MHz HCLK
  61         sleep 1
  62         mww 0x40023804 0x24001808                               ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
  63         mww 0x40023808 0x00001000                               ;# APB1: /2, APB2: /1
  64         mmw 0x40023800 0x01000000 0x00000000    ;# PLL on
  65         sleep 1
  66         mmw 0x40023808 0x00000002 0x00000000    ;# switch to PLL
  67         sleep 1
  68
  69         adapter speed 4000
  70
  71         qspi_init
  72 }