tcl/board/imx35pdk.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # The IMX35PDK eval board has a single IMX35 chip
   4 source [find target/imx35.cfg]
   5 source [find target/imx.cfg]
   6 $_TARGETNAME configure -event reset-init { imx35pdk_init }
   7
   8 # Stick to *really* low clock rate or reset will fail
   9 # without RTCK / RCLK
  10 jtag_rclk 10
  11
  12 proc imx35pdk_init { } {
  13
  14         imx3x_reset
  15
  16         mww 0x43f00040 0x00000000
  17         mww 0x43f00044 0x00000000
  18         mww 0x43f00048 0x00000000
  19         mww 0x43f0004C 0x00000000
  20         mww 0x43f00050 0x00000000
  21         mww 0x43f00000 0x77777777
  22         mww 0x43f00004 0x77777777
  23         mww 0x53f00040 0x00000000
  24         mww 0x53f00044 0x00000000
  25         mww 0x53f00048 0x00000000
  26         mww 0x53f0004C 0x00000000
  27         mww 0x53f00050 0x00000000
  28         mww 0x53f00000 0x77777777
  29         mww 0x53f00004 0x77777777
  30
  31         # clock setup
  32         mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
  33         mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
  34
  35         #=================================================
  36         # WEIM config
  37         #=================================================
  38         # CS0U
  39         mww 0xB8002000 0x0000CC03
  40         # CS0L
  41         mww 0xB8002004 0xA0330D01
  42         # CS0A
  43         mww 0xB8002008 0x00220800
  44         # CS5U
  45         mww 0xB8002050 0x0000dcf6
  46         # CS5L
  47         mww 0xB8002054 0x444a4541
  48         # CS5A
  49         mww 0xB8002058 0x44443302
  50
  51         # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
  52         mww 0x43FAC368 0x00000006
  53         mww 0x43FAC36C 0x00000006
  54         mww 0x43FAC370 0x00000006
  55         mww 0x43FAC374 0x00000006
  56         mww 0x43FAC378 0x00000006
  57         mww 0x43FAC37C 0x00000006
  58         mww 0x43FAC380 0x00000006
  59         mww 0x43FAC384 0x00000006
  60         mww 0x43FAC388 0x00000006
  61         mww 0x43FAC38C 0x00000006
  62         mww 0x43FAC390 0x00000006
  63         mww 0x43FAC394 0x00000006
  64         mww 0x43FAC398 0x00000006
  65         mww 0x43FAC39C 0x00000006
  66         mww 0x43FAC3A0 0x00000006
  67         mww 0x43FAC3A4 0x00000006
  68         mww 0x43FAC3A8 0x00000006
  69         mww 0x43FAC3AC 0x00000006
  70         mww 0x43FAC3B0 0x00000006
  71         mww 0x43FAC3B4 0x00000006
  72         mww 0x43FAC3B8 0x00000006
  73         mww 0x43FAC3BC 0x00000006
  74         mww 0x43FAC3C0 0x00000006
  75         mww 0x43FAC3C4 0x00000006
  76         mww 0x43FAC3C8 0x00000006
  77         mww 0x43FAC3CC 0x00000006
  78         mww 0x43FAC3D0 0x00000006
  79         mww 0x43FAC3D4 0x00000006
  80         mww 0x43FAC3D8 0x00000006
  81
  82         # DDR data bus SD 0 through 31
  83         mww 0x43FAC3DC 0x00000082
  84         mww 0x43FAC3E0 0x00000082
  85         mww 0x43FAC3E4 0x00000082
  86         mww 0x43FAC3E8 0x00000082
  87         mww 0x43FAC3EC 0x00000082
  88         mww 0x43FAC3F0 0x00000082
  89         mww 0x43FAC3F4 0x00000082
  90         mww 0x43FAC3F8 0x00000082
  91         mww 0x43FAC3FC 0x00000082
  92         mww 0x43FAC400 0x00000082
  93         mww 0x43FAC404 0x00000082
  94         mww 0x43FAC408 0x00000082
  95         mww 0x43FAC40C 0x00000082
  96         mww 0x43FAC410 0x00000082
  97         mww 0x43FAC414 0x00000082
  98         mww 0x43FAC418 0x00000082
  99         mww 0x43FAC41c 0x00000082
 100         mww 0x43FAC420 0x00000082
 101         mww 0x43FAC424 0x00000082
 102         mww 0x43FAC428 0x00000082
 103         mww 0x43FAC42c 0x00000082
 104         mww 0x43FAC430 0x00000082
 105         mww 0x43FAC434 0x00000082
 106         mww 0x43FAC438 0x00000082
 107         mww 0x43FAC43c 0x00000082
 108         mww 0x43FAC440 0x00000082
 109         mww 0x43FAC444 0x00000082
 110         mww 0x43FAC448 0x00000082
 111         mww 0x43FAC44c 0x00000082
 112         mww 0x43FAC450 0x00000082
 113         mww 0x43FAC454 0x00000082
 114         mww 0x43FAC458 0x00000082
 115
 116         # DQM setup
 117         mww 0x43FAC45c 0x00000082
 118         mww 0x43FAC460 0x00000082
 119         mww 0x43FAC464 0x00000082
 120         mww 0x43FAC468 0x00000082
 121
 122         mww 0x43FAC46c 0x00000006
 123         mww 0x43FAC470 0x00000006
 124         mww 0x43FAC474 0x00000006
 125         mww 0x43FAC478 0x00000006
 126         mww 0x43FAC47c 0x00000006
 127         mww 0x43FAC480 0x00000006       ;# CSD0
 128         mww 0x43FAC484 0x00000006       ;# CSD1
 129         mww 0x43FAC488 0x00000006
 130         mww 0x43FAC48c 0x00000006
 131         mww 0x43FAC490 0x00000006
 132         mww 0x43FAC494 0x00000006
 133         mww 0x43FAC498 0x00000006
 134         mww 0x43FAC49c 0x00000006
 135         mww 0x43FAC4A0 0x00000006
 136         mww 0x43FAC4A4 0x00000006       ;# RAS
 137         mww 0x43FAC4A8 0x00000006       ;# CAS
 138         mww 0x43FAC4Ac 0x00000006       ;# SDWE
 139         mww 0x43FAC4B0 0x00000006       ;# SDCKE0
 140         mww 0x43FAC4B4 0x00000006  ;# SDCKE1
 141         mww 0x43FAC4B8 0x00000002  ;# SDCLK
 142
 143         # SDQS0 through SDQS3
 144         mww 0x43FAC4Bc 0x00000082
 145         mww 0x43FAC4C0 0x00000082
 146         mww 0x43FAC4C4 0x00000082
 147         mww 0x43FAC4C8 0x00000082
 148
 149
 150         # *==================================================
 151         #  Initialization script for 32 bit DDR2 on RINGO 3DS
 152         # *==================================================
 153
 154         #--------------------------------------------
 155         # Init CCM
 156         #--------------------------------------------
 157         mww 0x53F80028 0x7D000028
 158
 159         #--------------------------------------------
 160         # Init IOMUX for JTAG
 161         #--------------------------------------------
 162         mww 0x43FAC5EC 0x000000C3
 163         mww 0x43FAC5F0 0x000000C3
 164         mww 0x43FAC5F4 0x000000F3
 165         mww 0x43FAC5F8 0x000000F3
 166         mww 0x43FAC5FC 0x000000F3
 167         mww 0x43FAC600 0x000000F3
 168         mww 0x43FAC604 0x000000F3
 169
 170
 171         # ESD_MISC : enable DDR2
 172         mww 0xB8001010 0x00000304
 173
 174         #--------------------------------------------
 175         # Init 32-bit DDR2 memory on CSD0
 176         # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 177         #--------------------------------------------
 178
 179         # ESD_ESDCFG0 : set timing parameters
 180         mww 0xB8001004 0x007ffC2f
 181
 182         # ESD_ESDCTL0 : select Prechare-All mode
 183         mww 0xB8001000 0x92220000
 184         # DDR2 : Prechare-All
 185         mww 0x80000400 0x12345678
 186
 187         # ESD_ESDCTL0 : select Load-Mode-Register mode
 188         mww 0xB8001000 0xB2220000
 189         # DDR2 : Load reg EMR2
 190         mwb 0x84000000 0xda
 191         # DDR2 : Load reg EMR3
 192         mwb 0x86000000 0xda
 193         # DDR2 : Load reg EMR1 -- enable DLL
 194         mwb 0x82000400 0xda
 195         # DDR2 : Load reg MR -- reset DLL
 196         mwb 0x80000333 0xda
 197
 198         # ESD_ESDCTL0 : select Prechare-All mode
 199         mww 0xB8001000 0x92220000
 200         # DDR2 : Prechare-All
 201         mwb 0x80000400 0x12345678
 202
 203         # ESD_ESDCTL0 : select Manual-Refresh mode
 204         mww 0xB8001000 0xA2220000
 205         # DDR2 : Manual-Refresh 2 times
 206         mww 0x80000000 0x87654321
 207         mww 0x80000000 0x87654321
 208
 209         # ESD_ESDCTL0 : select Load-Mode-Register mode
 210         mww 0xB8001000 0xB2220000
 211         # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
 212         mwb 0x80000233 0xda
 213         # DDR2 : Load reg EMR1 -- OCD default
 214         mwb 0x82000780 0xda
 215         # DDR2 : Load reg EMR1 -- OCD exit
 216         mwb 0x82000400 0xda     ;# ODT disabled
 217
 218         # ESD_ESDCTL0 : select normal-operation mode
 219         # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 220         # disable PWT & PRCT
 221         # disable Auto-Refresh
 222         mww 0xB8001000 0x82220080
 223
 224         ## ESD_ESDCTL0 : enable Auto-Refresh
 225         mww 0xB8001000 0x82228080
 226         ## ESD_ESDCTL1 : enable Auto-Refresh
 227         mww 0xB8001008 0x00002000
 228
 229
 230         #***********************************************
 231         # Adjust the ESDCDLY5 register
 232         #***********************************************
 233         # Vary DQS_ABS_OFFSET5 for writes
 234         mww 0xB8001020 0x00F48000       ;# this is the default value
 235         mww 0xB8001024 0x00F48000       ;# this is the default value
 236         mww 0xB8001028 0x00F48000       ;# this is the default value
 237         mww 0xB800102c 0x00F48000       ;# this is the default value
 238
 239
 240         #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 241         mww 0xB8001010 0x00000384
 242         # wait a while
 243         sleep 1000
 244         # now clear the force measurement bit
 245         mww 0xB8001010 0x00000304
 246
 247         # dummy write to DDR memory to set DQS low
 248         mww 0x80000000 0x00000000
 249
 250         mww 0x30000100 0x0
 251         mww 0x30000104 0x31024
 252
 253
 254 }