9 #include "target/target.h"
10 #include "target/algorithm.h"
11 #include "target/target_type.h"
13 #include "jtag/jtag.h"
14 #include "target/register.h"
15 #include "target/breakpoints.h"
16 #include "helper/time_support.h"
19 #include "rtos/rtos.h"
22 * Since almost everything can be accomplish by scanning the dbus register, all
23 * functions here assume dbus is already selected. The exception are functions
24 * called directly by OpenOCD, which can't assume anything about what's
25 * currently in IR. They should set IR to dbus explicitly.
31 * At the bottom of the stack are the OpenOCD JTAG functions:
36 * There are a few functions to just instantly shift a register and get its
42 * Because doing one scan and waiting for the result is slow, most functions
43 * batch up a bunch of dbus writes and then execute them all at once. They use
44 * the scans "class" for this:
49 * Usually you new(), call a bunch of add functions, then execute() and look
50 * at the results by calling scans_get...()
52 * Optimized functions will directly use the scans class above, but slightly
53 * lazier code will use the cache functions that in turn use the scans
58 * cache_set... update a local structure, which is then synced to the target
59 * with cache_write(). Only Debug RAM words that are actually changed are sent
60 * to the target. Afterwards use cache_get... to read results.
63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
66 #define DIM(x) (sizeof(x)/sizeof(*x))
68 /* Constants for legacy SiFive hardware breakpoints. */
69 #define CSR_BPCONTROL_X (1<<0)
70 #define CSR_BPCONTROL_W (1<<1)
71 #define CSR_BPCONTROL_R (1<<2)
72 #define CSR_BPCONTROL_U (1<<3)
73 #define CSR_BPCONTROL_S (1<<4)
74 #define CSR_BPCONTROL_H (1<<5)
75 #define CSR_BPCONTROL_M (1<<6)
76 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
77 #define CSR_BPCONTROL_BPACTION (0xff<<11)
79 #define DEBUG_ROM_START 0x800
80 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
81 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
82 #define DEBUG_RAM_START 0x400
84 #define SETHALTNOT 0x10c
86 /*** JTAG registers. ***/
88 #define DTMCONTROL 0x10
89 #define DTMCONTROL_DBUS_RESET (1<<16)
90 #define DTMCONTROL_IDLE (7<<10)
91 #define DTMCONTROL_ADDRBITS (0xf<<4)
92 #define DTMCONTROL_VERSION (0xf)
95 #define DBUS_OP_START 0
96 #define DBUS_OP_SIZE 2
103 DBUS_STATUS_SUCCESS
= 0,
104 DBUS_STATUS_FAILED
= 2,
107 #define DBUS_DATA_START 2
108 #define DBUS_DATA_SIZE 34
109 #define DBUS_ADDRESS_START 36
123 /*** Debug Bus registers. ***/
125 #define DMCONTROL 0x10
126 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
127 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
128 #define DMCONTROL_BUSERROR (7<<19)
129 #define DMCONTROL_SERIAL (3<<16)
130 #define DMCONTROL_AUTOINCREMENT (1<<15)
131 #define DMCONTROL_ACCESS (7<<12)
132 #define DMCONTROL_HARTID (0x3ff<<2)
133 #define DMCONTROL_NDRESET (1<<1)
134 #define DMCONTROL_FULLRESET 1
137 #define DMINFO_ABUSSIZE (0x7fU<<25)
138 #define DMINFO_SERIALCOUNT (0xf<<21)
139 #define DMINFO_ACCESS128 (1<<20)
140 #define DMINFO_ACCESS64 (1<<19)
141 #define DMINFO_ACCESS32 (1<<18)
142 #define DMINFO_ACCESS16 (1<<17)
143 #define DMINFO_ACCESS8 (1<<16)
144 #define DMINFO_DRAMSIZE (0x3f<<10)
145 #define DMINFO_AUTHENTICATED (1<<5)
146 #define DMINFO_AUTHBUSY (1<<4)
147 #define DMINFO_AUTHTYPE (3<<2)
148 #define DMINFO_VERSION 3
150 /*** Info about the core being debugged. ***/
152 #define DBUS_ADDRESS_UNKNOWN 0xffff
155 #define DRAM_CACHE_SIZE 16
157 uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
158 struct scan_field select_dtmcontrol
= {
160 .out_value
= ir_dtmcontrol
162 uint8_t ir_dbus
[4] = {DBUS
};
163 struct scan_field select_dbus
= {
167 uint8_t ir_idcode
[4] = {0x1};
168 struct scan_field select_idcode
= {
170 .out_value
= ir_idcode
178 bool read
, write
, execute
;
182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
183 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
186 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
188 bool riscv_prefer_sba
;
194 /* In addition to the ones in the standard spec, we'll also expose additional
196 * The list is either NULL, or a series of ranges (inclusive), terminated with
199 /* Same, but for custom registers. */
200 range_t
*expose_custom
;
202 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
204 struct scan_field field
;
206 uint8_t out_value
[4] = { 0 };
208 buf_set_u32(out_value
, 0, 32, out
);
210 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
213 field
.out_value
= out_value
;
214 field
.in_value
= in_value
;
215 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
217 /* Always return to dbus. */
218 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
220 int retval
= jtag_execute_queue();
221 if (retval
!= ERROR_OK
) {
222 LOG_ERROR("failed jtag scan: %d", retval
);
226 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
227 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
232 static struct target_type
*get_target_type(struct target
*target
)
234 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
237 LOG_ERROR("Target has not been initialized");
241 switch (info
->dtm_version
) {
243 return &riscv011_target
;
245 return &riscv013_target
;
247 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
252 static int riscv_init_target(struct command_context
*cmd_ctx
,
253 struct target
*target
)
255 LOG_DEBUG("riscv_init_target()");
256 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
257 if (!target
->arch_info
)
259 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
260 riscv_info_init(target
, info
);
261 info
->cmd_ctx
= cmd_ctx
;
263 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
264 select_dbus
.num_bits
= target
->tap
->ir_length
;
265 select_idcode
.num_bits
= target
->tap
->ir_length
;
267 riscv_semihosting_init(target
);
269 target
->debug_reason
= DBG_REASON_DBGRQ
;
274 static void riscv_free_registers(struct target
*target
)
276 /* Free the shared structure use for most registers. */
277 if (target
->reg_cache
) {
278 if (target
->reg_cache
->reg_list
) {
279 free(target
->reg_cache
->reg_list
[0].arch_info
);
280 /* Free the ones we allocated separately. */
281 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
282 free(target
->reg_cache
->reg_list
[i
].arch_info
);
283 free(target
->reg_cache
->reg_list
);
285 free(target
->reg_cache
);
289 static void riscv_deinit_target(struct target
*target
)
291 LOG_DEBUG("riscv_deinit_target()");
292 struct target_type
*tt
= get_target_type(target
);
294 tt
->deinit_target(target
);
295 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
296 free(info
->reg_names
);
300 riscv_free_registers(target
);
302 target
->arch_info
= NULL
;
305 static int oldriscv_halt(struct target
*target
)
307 struct target_type
*tt
= get_target_type(target
);
308 return tt
->halt(target
);
311 static void trigger_from_breakpoint(struct trigger
*trigger
,
312 const struct breakpoint
*breakpoint
)
314 trigger
->address
= breakpoint
->address
;
315 trigger
->length
= breakpoint
->length
;
316 trigger
->mask
= ~0LL;
317 trigger
->read
= false;
318 trigger
->write
= false;
319 trigger
->execute
= true;
320 /* unique_id is unique across both breakpoints and watchpoints. */
321 trigger
->unique_id
= breakpoint
->unique_id
;
324 static int maybe_add_trigger_t1(struct target
*target
, unsigned hartid
,
325 struct trigger
*trigger
, uint64_t tdata1
)
329 const uint32_t bpcontrol_x
= 1<<0;
330 const uint32_t bpcontrol_w
= 1<<1;
331 const uint32_t bpcontrol_r
= 1<<2;
332 const uint32_t bpcontrol_u
= 1<<3;
333 const uint32_t bpcontrol_s
= 1<<4;
334 const uint32_t bpcontrol_h
= 1<<5;
335 const uint32_t bpcontrol_m
= 1<<6;
336 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
337 const uint32_t bpcontrol_bpaction
= 0xff << 11;
339 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
340 /* Trigger is already in use, presumably by user code. */
341 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
344 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
345 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
346 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
347 tdata1
= set_field(tdata1
, bpcontrol_u
,
348 !!(r
->misa
[hartid
] & (1 << ('U' - 'A'))));
349 tdata1
= set_field(tdata1
, bpcontrol_s
,
350 !!(r
->misa
[hartid
] & (1 << ('S' - 'A'))));
351 tdata1
= set_field(tdata1
, bpcontrol_h
,
352 !!(r
->misa
[hartid
] & (1 << ('H' - 'A'))));
353 tdata1
|= bpcontrol_m
;
354 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
355 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
357 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
359 riscv_reg_t tdata1_rb
;
360 if (riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
,
361 GDB_REGNO_TDATA1
) != ERROR_OK
)
363 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
365 if (tdata1
!= tdata1_rb
) {
366 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
367 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
369 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
370 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
373 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
378 static int maybe_add_trigger_t2(struct target
*target
, unsigned hartid
,
379 struct trigger
*trigger
, uint64_t tdata1
)
383 /* tselect is already set */
384 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
385 /* Trigger is already in use, presumably by user code. */
386 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
389 /* address/data match trigger */
390 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
391 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
392 MCONTROL_ACTION_DEBUG_MODE
);
393 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
394 tdata1
|= MCONTROL_M
;
395 if (r
->misa
[hartid
] & (1 << ('H' - 'A')))
396 tdata1
|= MCONTROL_H
;
397 if (r
->misa
[hartid
] & (1 << ('S' - 'A')))
398 tdata1
|= MCONTROL_S
;
399 if (r
->misa
[hartid
] & (1 << ('U' - 'A')))
400 tdata1
|= MCONTROL_U
;
402 if (trigger
->execute
)
403 tdata1
|= MCONTROL_EXECUTE
;
405 tdata1
|= MCONTROL_LOAD
;
407 tdata1
|= MCONTROL_STORE
;
409 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
412 int result
= riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
, GDB_REGNO_TDATA1
);
413 if (result
!= ERROR_OK
)
415 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
417 if (tdata1
!= tdata1_rb
) {
418 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
419 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
421 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
425 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
430 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
434 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
437 /* In RTOS mode, we need to set the same trigger in the same slot on every
438 * hart, to keep up the illusion that each hart is a thread running on the
441 /* Otherwise, we just set the trigger on the one hart this target deals
444 riscv_reg_t tselect
[RISCV_MAX_HARTS
];
447 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
448 if (!riscv_hart_enabled(target
, hartid
))
452 int result
= riscv_get_register_on_hart(target
, &tselect
[hartid
],
453 hartid
, GDB_REGNO_TSELECT
);
454 if (result
!= ERROR_OK
)
457 assert(first_hart
>= 0);
460 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
461 if (r
->trigger_unique_id
[i
] != -1)
464 riscv_set_register_on_hart(target
, first_hart
, GDB_REGNO_TSELECT
, i
);
467 int result
= riscv_get_register_on_hart(target
, &tdata1
, first_hart
,
469 if (result
!= ERROR_OK
)
471 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
474 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
475 if (!riscv_hart_enabled(target
, hartid
))
477 if (hartid
> first_hart
)
478 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
481 result
= maybe_add_trigger_t1(target
, hartid
, trigger
, tdata1
);
484 result
= maybe_add_trigger_t2(target
, hartid
, trigger
, tdata1
);
487 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
491 if (result
!= ERROR_OK
)
495 if (result
!= ERROR_OK
)
498 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
499 i
, type
, trigger
->unique_id
);
500 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
504 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
505 if (!riscv_hart_enabled(target
, hartid
))
507 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
,
511 if (i
>= r
->trigger_count
[first_hart
]) {
512 LOG_ERROR("Couldn't find an available hardware trigger.");
513 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
519 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
521 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
523 if (breakpoint
->type
== BKPT_SOFT
) {
524 /** @todo check RVC for size/alignment */
525 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
526 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
530 if (0 != (breakpoint
->address
% 2)) {
531 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
535 if (target_read_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
536 breakpoint
->orig_instr
) != ERROR_OK
) {
537 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
538 breakpoint
->address
);
542 uint8_t buff
[4] = { 0 };
543 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
544 int const retval
= target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2, buff
);
546 if (retval
!= ERROR_OK
) {
547 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
548 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
552 } else if (breakpoint
->type
== BKPT_HARD
) {
553 struct trigger trigger
;
554 trigger_from_breakpoint(&trigger
, breakpoint
);
555 int const result
= add_trigger(target
, &trigger
);
556 if (result
!= ERROR_OK
)
559 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
560 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
563 breakpoint
->set
= true;
567 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
571 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
575 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
576 if (!riscv_hart_enabled(target
, hartid
))
578 if (first_hart
< 0) {
583 assert(first_hart
>= 0);
586 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
587 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
590 if (i
>= r
->trigger_count
[first_hart
]) {
591 LOG_ERROR("Couldn't find the hardware resources used by hardware "
595 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
597 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
598 if (!riscv_hart_enabled(target
, hartid
))
601 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
, GDB_REGNO_TSELECT
);
602 if (result
!= ERROR_OK
)
604 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
605 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
606 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
608 r
->trigger_unique_id
[i
] = -1;
613 int riscv_remove_breakpoint(struct target
*target
,
614 struct breakpoint
*breakpoint
)
616 if (breakpoint
->type
== BKPT_SOFT
) {
617 if (target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
618 breakpoint
->orig_instr
) != ERROR_OK
) {
619 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
620 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
624 } else if (breakpoint
->type
== BKPT_HARD
) {
625 struct trigger trigger
;
626 trigger_from_breakpoint(&trigger
, breakpoint
);
627 int result
= remove_trigger(target
, &trigger
);
628 if (result
!= ERROR_OK
)
632 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
633 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
636 breakpoint
->set
= false;
641 static void trigger_from_watchpoint(struct trigger
*trigger
,
642 const struct watchpoint
*watchpoint
)
644 trigger
->address
= watchpoint
->address
;
645 trigger
->length
= watchpoint
->length
;
646 trigger
->mask
= watchpoint
->mask
;
647 trigger
->value
= watchpoint
->value
;
648 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
649 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
650 trigger
->execute
= false;
651 /* unique_id is unique across both breakpoints and watchpoints. */
652 trigger
->unique_id
= watchpoint
->unique_id
;
655 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
657 struct trigger trigger
;
658 trigger_from_watchpoint(&trigger
, watchpoint
);
660 int result
= add_trigger(target
, &trigger
);
661 if (result
!= ERROR_OK
)
663 watchpoint
->set
= true;
668 int riscv_remove_watchpoint(struct target
*target
,
669 struct watchpoint
*watchpoint
)
671 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
673 struct trigger trigger
;
674 trigger_from_watchpoint(&trigger
, watchpoint
);
676 int result
= remove_trigger(target
, &trigger
);
677 if (result
!= ERROR_OK
)
679 watchpoint
->set
= false;
684 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
687 * The GDB server uses this information to tell GDB what data address has
688 * been hit, which enables GDB to print the hit variable along with its old
690 int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
692 struct watchpoint
*wp
= target
->watchpoints
;
694 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
696 /*TODO instead of disassembling the instruction that we think caused the
697 * trigger, check the hit bit of each watchpoint first. The hit bit is
698 * simpler and more reliable to check but as it is optional and relatively
699 * new, not all hardware will implement it */
701 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
702 const uint8_t length
= 4;
703 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
705 /* fetch the instruction at dpc */
706 uint8_t buffer
[length
];
707 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
708 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
712 uint32_t instruction
= 0;
714 for (int i
= 0; i
< length
; i
++) {
715 LOG_DEBUG("Next byte is %x", buffer
[i
]);
716 instruction
+= (buffer
[i
] << 8 * i
);
718 LOG_DEBUG("Full instruction is %x", instruction
);
720 /* find out which memory address is accessed by the instruction at dpc */
721 /* opcode is first 7 bits of the instruction */
722 uint8_t opcode
= instruction
& 0x7F;
725 riscv_reg_t mem_addr
;
727 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
728 rs1
= (instruction
& 0xf8000) >> 15;
729 riscv_get_register(target
, &mem_addr
, rs1
);
731 if (opcode
== MATCH_SB
) {
732 LOG_DEBUG("%x is store instruction", instruction
);
733 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
735 LOG_DEBUG("%x is load instruction", instruction
);
736 imm
= (instruction
& 0xfff00000) >> 20;
738 /* sign extend 12-bit imm to 16-bits */
742 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
744 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
749 /*TODO support length/mask */
750 if (wp
->address
== mem_addr
) {
751 *hit_watchpoint
= wp
;
752 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
758 /* No match found - either we hit a watchpoint caused by an instruction that
759 * this function does not yet disassemble, or we hit a breakpoint.
761 * OpenOCD will behave as if this function had never been implemented i.e.
762 * report the halt to GDB with no address information. */
767 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
768 int handle_breakpoints
)
770 struct target_type
*tt
= get_target_type(target
);
771 return tt
->step(target
, current
, address
, handle_breakpoints
);
774 static int old_or_new_riscv_step(struct target
*target
, int current
,
775 target_addr_t address
, int handle_breakpoints
)
778 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
779 if (r
->is_halted
== NULL
)
780 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
782 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
786 static int riscv_examine(struct target
*target
)
788 LOG_DEBUG("riscv_examine()");
789 if (target_was_examined(target
)) {
790 LOG_DEBUG("Target was already examined.");
794 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
796 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
797 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
798 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
799 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
800 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
802 struct target_type
*tt
= get_target_type(target
);
806 int result
= tt
->init_target(info
->cmd_ctx
, target
);
807 if (result
!= ERROR_OK
)
810 return tt
->examine(target
);
813 static int oldriscv_poll(struct target
*target
)
815 struct target_type
*tt
= get_target_type(target
);
816 return tt
->poll(target
);
819 static int old_or_new_riscv_poll(struct target
*target
)
822 if (r
->is_halted
== NULL
)
823 return oldriscv_poll(target
);
825 return riscv_openocd_poll(target
);
828 static int old_or_new_riscv_halt(struct target
*target
)
831 if (r
->is_halted
== NULL
)
832 return oldriscv_halt(target
);
834 return riscv_openocd_halt(target
);
837 static int riscv_assert_reset(struct target
*target
)
839 LOG_DEBUG("[%d]", target
->coreid
);
840 struct target_type
*tt
= get_target_type(target
);
841 riscv_invalidate_register_cache(target
);
842 return tt
->assert_reset(target
);
845 static int riscv_deassert_reset(struct target
*target
)
847 LOG_DEBUG("[%d]", target
->coreid
);
848 struct target_type
*tt
= get_target_type(target
);
849 return tt
->deassert_reset(target
);
853 static int oldriscv_resume(struct target
*target
, int current
, uint32_t address
,
854 int handle_breakpoints
, int debug_execution
)
856 struct target_type
*tt
= get_target_type(target
);
857 return tt
->resume(target
, current
, address
, handle_breakpoints
,
861 static int old_or_new_riscv_resume(struct target
*target
, int current
,
862 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
864 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
866 struct target_list
*targets
= target
->head
;
867 int result
= ERROR_OK
;
869 struct target
*t
= targets
->target
;
870 riscv_info_t
*r
= riscv_info(t
);
871 if (r
->is_halted
== NULL
) {
872 if (oldriscv_resume(t
, current
, address
, handle_breakpoints
,
873 debug_execution
) != ERROR_OK
)
876 if (riscv_openocd_resume(t
, current
, address
,
877 handle_breakpoints
, debug_execution
) != ERROR_OK
)
880 targets
= targets
->next
;
886 if (r
->is_halted
== NULL
)
887 return oldriscv_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
889 return riscv_openocd_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
892 static int riscv_select_current_hart(struct target
*target
)
895 if (riscv_rtos_enabled(target
)) {
896 if (r
->rtos_hartid
== -1)
897 r
->rtos_hartid
= target
->rtos
->current_threadid
- 1;
898 return riscv_set_current_hartid(target
, r
->rtos_hartid
);
900 return riscv_set_current_hartid(target
, target
->coreid
);
903 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
904 uint32_t size
, uint32_t count
, uint8_t *buffer
)
906 if (riscv_select_current_hart(target
) != ERROR_OK
)
908 struct target_type
*tt
= get_target_type(target
);
909 return tt
->read_memory(target
, address
, size
, count
, buffer
);
912 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
913 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
915 if (riscv_select_current_hart(target
) != ERROR_OK
)
917 struct target_type
*tt
= get_target_type(target
);
918 return tt
->write_memory(target
, address
, size
, count
, buffer
);
921 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
922 struct reg
**reg_list
[], int *reg_list_size
,
923 enum target_register_class reg_class
, bool read
)
926 LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
927 r
->rtos_hartid
, r
->current_hartid
, reg_class
, read
);
929 if (!target
->reg_cache
) {
930 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
934 if (riscv_select_current_hart(target
) != ERROR_OK
)
938 case REG_CLASS_GENERAL
:
942 *reg_list_size
= target
->reg_cache
->num_regs
;
945 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
949 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
953 for (int i
= 0; i
< *reg_list_size
; i
++) {
954 assert(!target
->reg_cache
->reg_list
[i
].valid
||
955 target
->reg_cache
->reg_list
[i
].size
> 0);
956 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
957 if (read
&& !target
->reg_cache
->reg_list
[i
].valid
) {
958 if (target
->reg_cache
->reg_list
[i
].type
->get(
959 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
960 /* This function is called when first connecting to gdb,
961 * resulting in an attempt to read all kinds of registers which
962 * probably will fail. Ignore these failures, and when
963 * encountered stop reading to save time. */
971 static int riscv_get_gdb_reg_list(struct target
*target
,
972 struct reg
**reg_list
[], int *reg_list_size
,
973 enum target_register_class reg_class
)
975 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
979 static int riscv_arch_state(struct target
*target
)
981 struct target_type
*tt
= get_target_type(target
);
982 return tt
->arch_state(target
);
985 /* Algorithm must end with a software breakpoint instruction. */
986 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
987 struct mem_param
*mem_params
, int num_reg_params
,
988 struct reg_param
*reg_params
, target_addr_t entry_point
,
989 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
991 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
993 if (num_mem_params
> 0) {
994 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
998 if (target
->state
!= TARGET_HALTED
) {
999 LOG_WARNING("target not halted");
1000 return ERROR_TARGET_NOT_HALTED
;
1003 /* Save registers */
1004 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", 1);
1005 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1007 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1009 uint64_t saved_regs
[32];
1010 for (int i
= 0; i
< num_reg_params
; i
++) {
1011 if (reg_params
[i
].direction
== PARAM_IN
)
1014 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1015 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1017 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1021 if (r
->size
!= reg_params
[i
].size
) {
1022 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1023 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1027 if (r
->number
> GDB_REGNO_XPR31
) {
1028 LOG_ERROR("Only GPRs can be use as argument registers.");
1032 if (r
->type
->get(r
) != ERROR_OK
)
1034 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1035 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1040 /* Disable Interrupts before attempting to run the algorithm. */
1041 uint64_t current_mstatus
;
1042 uint8_t mstatus_bytes
[8] = { 0 };
1044 LOG_DEBUG("Disabling Interrupts");
1045 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1048 LOG_ERROR("Couldn't find mstatus!");
1052 reg_mstatus
->type
->get(reg_mstatus
);
1053 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1054 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1055 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], set_field(current_mstatus
,
1058 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1061 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1062 if (oldriscv_resume(target
, 0, entry_point
, 0, 0) != ERROR_OK
)
1065 int64_t start
= timeval_ms();
1066 while (target
->state
!= TARGET_HALTED
) {
1067 LOG_DEBUG("poll()");
1068 int64_t now
= timeval_ms();
1069 if (now
- start
> timeout_ms
) {
1070 LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms
);
1071 LOG_ERROR(" now = 0x%08x", (uint32_t) now
);
1072 LOG_ERROR(" start = 0x%08x", (uint32_t) start
);
1073 oldriscv_halt(target
);
1074 old_or_new_riscv_poll(target
);
1075 return ERROR_TARGET_TIMEOUT
;
1078 int result
= old_or_new_riscv_poll(target
);
1079 if (result
!= ERROR_OK
)
1083 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1085 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1086 if (final_pc
!= exit_point
) {
1087 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1088 TARGET_PRIxADDR
, final_pc
, exit_point
);
1092 /* Restore Interrupts */
1093 LOG_DEBUG("Restoring Interrupts");
1094 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], current_mstatus
);
1095 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1097 /* Restore registers */
1098 uint8_t buf
[8] = { 0 };
1099 buf_set_u64(buf
, 0, info
->xlen
[0], saved_pc
);
1100 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1103 for (int i
= 0; i
< num_reg_params
; i
++) {
1104 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1105 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1106 buf_set_u64(buf
, 0, info
->xlen
[0], saved_regs
[r
->number
]);
1107 if (r
->type
->set(r
, buf
) != ERROR_OK
)
1114 /* Should run code on the target to perform CRC of
1115 memory. Not yet implemented.
1118 static int riscv_checksum_memory(struct target
*target
,
1119 target_addr_t address
, uint32_t count
,
1122 *checksum
= 0xFFFFFFFF;
1123 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1126 /*** OpenOCD Helper Functions ***/
1128 enum riscv_poll_hart
{
1130 RPH_DISCOVERED_HALTED
,
1131 RPH_DISCOVERED_RUNNING
,
1134 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
1137 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1140 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
1142 /* If OpenOCD thinks we're running but this hart is halted then it's time
1143 * to raise an event. */
1144 bool halted
= riscv_is_halted(target
);
1145 if (target
->state
!= TARGET_HALTED
&& halted
) {
1146 LOG_DEBUG(" triggered a halt");
1148 return RPH_DISCOVERED_HALTED
;
1149 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
1150 LOG_DEBUG(" triggered running");
1151 target
->state
= TARGET_RUNNING
;
1152 return RPH_DISCOVERED_RUNNING
;
1155 return RPH_NO_CHANGE
;
1158 int set_debug_reason(struct target
*target
, int hartid
)
1160 switch (riscv_halt_reason(target
, hartid
)) {
1161 case RISCV_HALT_BREAKPOINT
:
1162 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1164 case RISCV_HALT_TRIGGER
:
1165 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1167 case RISCV_HALT_INTERRUPT
:
1168 target
->debug_reason
= DBG_REASON_DBGRQ
;
1170 case RISCV_HALT_SINGLESTEP
:
1171 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1173 case RISCV_HALT_UNKNOWN
:
1174 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1176 case RISCV_HALT_ERROR
:
1182 /*** OpenOCD Interface ***/
1183 int riscv_openocd_poll(struct target
*target
)
1185 LOG_DEBUG("polling all harts");
1186 int halted_hart
= -1;
1187 if (riscv_rtos_enabled(target
)) {
1188 /* Check every hart for an event. */
1189 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1190 enum riscv_poll_hart out
= riscv_poll_hart(target
, i
);
1193 case RPH_DISCOVERED_RUNNING
:
1195 case RPH_DISCOVERED_HALTED
:
1202 if (halted_hart
== -1) {
1203 LOG_DEBUG(" no harts just halted, target->state=%d", target
->state
);
1206 LOG_DEBUG(" hart %d halted", halted_hart
);
1208 /* If we're here then at least one hart triggered. That means
1209 * we want to go and halt _every_ hart in the system, as that's
1210 * the invariant we hold here. Some harts might have already
1211 * halted (as we're either in single-step mode or they also
1212 * triggered a breakpoint), so don't attempt to halt those
1214 for (int i
= 0; i
< riscv_count_harts(target
); ++i
)
1215 riscv_halt_one_hart(target
, i
);
1217 } else if (target
->smp
) {
1218 bool halt_discovered
= false;
1219 bool newly_halted
[128] = {0};
1221 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1222 list
= list
->next
, i
++) {
1223 struct target
*t
= list
->target
;
1224 riscv_info_t
*r
= riscv_info(t
);
1225 assert(i
< DIM(newly_halted
));
1226 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
1230 case RPH_DISCOVERED_RUNNING
:
1231 t
->state
= TARGET_RUNNING
;
1233 case RPH_DISCOVERED_HALTED
:
1234 halt_discovered
= true;
1235 newly_halted
[i
] = true;
1236 t
->state
= TARGET_HALTED
;
1237 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1245 if (halt_discovered
) {
1246 LOG_DEBUG("Halt other targets in this SMP group.");
1248 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1249 list
= list
->next
, i
++) {
1250 struct target
*t
= list
->target
;
1251 riscv_info_t
*r
= riscv_info(t
);
1252 if (t
->state
!= TARGET_HALTED
) {
1253 if (riscv_halt_one_hart(t
, r
->current_hartid
) != ERROR_OK
)
1255 t
->state
= TARGET_HALTED
;
1256 if (set_debug_reason(t
, r
->current_hartid
) != ERROR_OK
)
1258 newly_halted
[i
] = true;
1262 /* Now that we have all our ducks in a row, tell the higher layers
1263 * what just happened. */
1265 for (struct target_list
*list
= target
->head
; list
!= NULL
;
1266 list
= list
->next
, i
++) {
1267 struct target
*t
= list
->target
;
1268 if (newly_halted
[i
])
1269 target_call_event_callbacks(t
, TARGET_EVENT_HALTED
);
1275 enum riscv_poll_hart out
= riscv_poll_hart(target
,
1276 riscv_current_hartid(target
));
1277 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
)
1279 else if (out
== RPH_ERROR
)
1282 halted_hart
= riscv_current_hartid(target
);
1283 LOG_DEBUG(" hart %d halted", halted_hart
);
1286 target
->state
= TARGET_HALTED
;
1287 if (set_debug_reason(target
, halted_hart
) != ERROR_OK
)
1290 if (riscv_rtos_enabled(target
)) {
1291 target
->rtos
->current_threadid
= halted_hart
+ 1;
1292 target
->rtos
->current_thread
= halted_hart
+ 1;
1293 riscv_set_rtos_hartid(target
, halted_hart
);
1296 target
->state
= TARGET_HALTED
;
1298 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
1300 if (riscv_semihosting(target
, &retval
) != 0)
1304 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1308 int riscv_openocd_halt(struct target
*target
)
1313 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1316 LOG_DEBUG("Halt other targets in this SMP group.");
1317 struct target_list
*targets
= target
->head
;
1320 struct target
*t
= targets
->target
;
1321 targets
= targets
->next
;
1322 if (t
->state
!= TARGET_HALTED
) {
1323 if (riscv_halt_all_harts(t
) != ERROR_OK
)
1324 result
= ERROR_FAIL
;
1328 result
= riscv_halt_all_harts(target
);
1331 if (riscv_rtos_enabled(target
)) {
1332 if (r
->rtos_hartid
!= -1) {
1333 LOG_DEBUG("halt requested on RTOS hartid %d", r
->rtos_hartid
);
1334 target
->rtos
->current_threadid
= r
->rtos_hartid
+ 1;
1335 target
->rtos
->current_thread
= r
->rtos_hartid
+ 1;
1337 LOG_DEBUG("halt requested, but no known RTOS hartid");
1340 target
->state
= TARGET_HALTED
;
1341 target
->debug_reason
= DBG_REASON_DBGRQ
;
1342 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1346 int riscv_openocd_resume(
1347 struct target
*target
,
1349 target_addr_t address
,
1350 int handle_breakpoints
,
1351 int debug_execution
)
1353 LOG_DEBUG("debug_reason=%d", target
->debug_reason
);
1356 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1358 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1359 /* To be able to run off a trigger, disable all the triggers, step, and
1360 * then resume as usual. */
1361 struct watchpoint
*watchpoint
= target
->watchpoints
;
1362 bool trigger_temporarily_cleared
[RISCV_MAX_HWBPS
] = {0};
1365 int result
= ERROR_OK
;
1366 while (watchpoint
&& result
== ERROR_OK
) {
1367 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1368 trigger_temporarily_cleared
[i
] = watchpoint
->set
;
1369 if (watchpoint
->set
)
1370 result
= riscv_remove_watchpoint(target
, watchpoint
);
1371 watchpoint
= watchpoint
->next
;
1375 if (result
== ERROR_OK
)
1376 result
= riscv_step_rtos_hart(target
);
1378 watchpoint
= target
->watchpoints
;
1380 while (watchpoint
) {
1381 LOG_DEBUG("watchpoint %d: cleared=%d", i
, trigger_temporarily_cleared
[i
]);
1382 if (trigger_temporarily_cleared
[i
]) {
1383 if (result
== ERROR_OK
)
1384 result
= riscv_add_watchpoint(target
, watchpoint
);
1386 riscv_add_watchpoint(target
, watchpoint
);
1388 watchpoint
= watchpoint
->next
;
1392 if (result
!= ERROR_OK
)
1396 int out
= riscv_resume_all_harts(target
);
1397 if (out
!= ERROR_OK
) {
1398 LOG_ERROR("unable to resume all harts");
1402 register_cache_invalidate(target
->reg_cache
);
1403 target
->state
= TARGET_RUNNING
;
1404 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1408 int riscv_openocd_step(struct target
*target
, int current
,
1409 target_addr_t address
, int handle_breakpoints
)
1411 LOG_DEBUG("stepping rtos hart");
1414 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1416 int out
= riscv_step_rtos_hart(target
);
1417 if (out
!= ERROR_OK
) {
1418 LOG_ERROR("unable to step rtos hart");
1422 register_cache_invalidate(target
->reg_cache
);
1423 target
->state
= TARGET_RUNNING
;
1424 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1425 target
->state
= TARGET_HALTED
;
1426 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1427 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1431 /* Command Handlers */
1432 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
1434 if (CMD_ARGC
!= 1) {
1435 LOG_ERROR("Command takes exactly 1 parameter");
1436 return ERROR_COMMAND_SYNTAX_ERROR
;
1438 int timeout
= atoi(CMD_ARGV
[0]);
1440 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1444 riscv_command_timeout_sec
= timeout
;
1449 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
1451 if (CMD_ARGC
!= 1) {
1452 LOG_ERROR("Command takes exactly 1 parameter");
1453 return ERROR_COMMAND_SYNTAX_ERROR
;
1455 int timeout
= atoi(CMD_ARGV
[0]);
1457 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1461 riscv_reset_timeout_sec
= timeout
;
1465 COMMAND_HANDLER(riscv_test_compliance
) {
1467 struct target
*target
= get_current_target(CMD_CTX
);
1472 LOG_ERROR("Command does not take any parameters.");
1473 return ERROR_COMMAND_SYNTAX_ERROR
;
1476 if (r
->test_compliance
) {
1477 return r
->test_compliance(target
);
1479 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
1484 COMMAND_HANDLER(riscv_set_prefer_sba
)
1486 if (CMD_ARGC
!= 1) {
1487 LOG_ERROR("Command takes exactly 1 parameter");
1488 return ERROR_COMMAND_SYNTAX_ERROR
;
1490 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_prefer_sba
);
1494 void parse_error(const char *string
, char c
, unsigned position
)
1496 char buf
[position
+2];
1497 for (unsigned i
= 0; i
< position
; i
++)
1499 buf
[position
] = '^';
1500 buf
[position
+ 1] = 0;
1502 LOG_ERROR("Parse error at character %c in:", c
);
1503 LOG_ERROR("%s", string
);
1504 LOG_ERROR("%s", buf
);
1507 int parse_ranges(range_t
**ranges
, const char **argv
)
1509 for (unsigned pass
= 0; pass
< 2; pass
++) {
1512 bool parse_low
= true;
1514 for (unsigned i
= 0; i
== 0 || argv
[0][i
-1]; i
++) {
1515 char c
= argv
[0][i
];
1517 /* Ignore whitespace. */
1525 } else if (c
== '-') {
1527 } else if (c
== ',' || c
== 0) {
1529 (*ranges
)[range
].low
= low
;
1530 (*ranges
)[range
].high
= low
;
1535 parse_error(argv
[0], c
, i
);
1536 return ERROR_COMMAND_SYNTAX_ERROR
;
1543 } else if (c
== ',' || c
== 0) {
1546 (*ranges
)[range
].low
= low
;
1547 (*ranges
)[range
].high
= high
;
1553 parse_error(argv
[0], c
, i
);
1554 return ERROR_COMMAND_SYNTAX_ERROR
;
1561 *ranges
= calloc(range
+ 2, sizeof(range_t
));
1563 (*ranges
)[range
].low
= 1;
1564 (*ranges
)[range
].high
= 0;
1571 COMMAND_HANDLER(riscv_set_expose_csrs
)
1573 if (CMD_ARGC
!= 1) {
1574 LOG_ERROR("Command takes exactly 1 parameter");
1575 return ERROR_COMMAND_SYNTAX_ERROR
;
1578 return parse_ranges(&expose_csr
, CMD_ARGV
);
1581 COMMAND_HANDLER(riscv_set_expose_custom
)
1583 if (CMD_ARGC
!= 1) {
1584 LOG_ERROR("Command takes exactly 1 parameter");
1585 return ERROR_COMMAND_SYNTAX_ERROR
;
1588 return parse_ranges(&expose_custom
, CMD_ARGV
);
1591 COMMAND_HANDLER(riscv_authdata_read
)
1593 if (CMD_ARGC
!= 0) {
1594 LOG_ERROR("Command takes no parameters");
1595 return ERROR_COMMAND_SYNTAX_ERROR
;
1598 struct target
*target
= get_current_target(CMD_CTX
);
1600 LOG_ERROR("target is NULL!");
1606 LOG_ERROR("riscv_info is NULL!");
1610 if (r
->authdata_read
) {
1612 if (r
->authdata_read(target
, &value
) != ERROR_OK
)
1614 command_print(CMD
, "0x%" PRIx32
, value
);
1617 LOG_ERROR("authdata_read is not implemented for this target.");
1622 COMMAND_HANDLER(riscv_authdata_write
)
1624 if (CMD_ARGC
!= 1) {
1625 LOG_ERROR("Command takes exactly 1 argument");
1626 return ERROR_COMMAND_SYNTAX_ERROR
;
1629 struct target
*target
= get_current_target(CMD_CTX
);
1633 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
1635 if (r
->authdata_write
) {
1636 return r
->authdata_write(target
, value
);
1638 LOG_ERROR("authdata_write is not implemented for this target.");
1643 COMMAND_HANDLER(riscv_dmi_read
)
1645 if (CMD_ARGC
!= 1) {
1646 LOG_ERROR("Command takes 1 parameter");
1647 return ERROR_COMMAND_SYNTAX_ERROR
;
1650 struct target
*target
= get_current_target(CMD_CTX
);
1652 LOG_ERROR("target is NULL!");
1658 LOG_ERROR("riscv_info is NULL!");
1663 uint32_t address
, value
;
1664 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1665 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
1667 command_print(CMD
, "0x%" PRIx32
, value
);
1670 LOG_ERROR("dmi_read is not implemented for this target.");
1676 COMMAND_HANDLER(riscv_dmi_write
)
1678 if (CMD_ARGC
!= 2) {
1679 LOG_ERROR("Command takes exactly 2 arguments");
1680 return ERROR_COMMAND_SYNTAX_ERROR
;
1683 struct target
*target
= get_current_target(CMD_CTX
);
1686 uint32_t address
, value
;
1687 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1688 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1691 return r
->dmi_write(target
, address
, value
);
1693 LOG_ERROR("dmi_write is not implemented for this target.");
1698 COMMAND_HANDLER(riscv_test_sba_config_reg
)
1700 if (CMD_ARGC
!= 4) {
1701 LOG_ERROR("Command takes exactly 4 arguments");
1702 return ERROR_COMMAND_SYNTAX_ERROR
;
1705 struct target
*target
= get_current_target(CMD_CTX
);
1708 target_addr_t legal_address
;
1710 target_addr_t illegal_address
;
1711 bool run_sbbusyerror_test
;
1713 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[0], legal_address
);
1714 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], num_words
);
1715 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[2], illegal_address
);
1716 COMMAND_PARSE_ON_OFF(CMD_ARGV
[3], run_sbbusyerror_test
);
1718 if (r
->test_sba_config_reg
) {
1719 return r
->test_sba_config_reg(target
, legal_address
, num_words
,
1720 illegal_address
, run_sbbusyerror_test
);
1722 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
1727 COMMAND_HANDLER(riscv_reset_delays
)
1732 LOG_ERROR("Command takes at most one argument");
1733 return ERROR_COMMAND_SYNTAX_ERROR
;
1737 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
1739 struct target
*target
= get_current_target(CMD_CTX
);
1741 r
->reset_delays_wait
= wait
;
1745 COMMAND_HANDLER(riscv_set_ir
)
1747 if (CMD_ARGC
!= 2) {
1748 LOG_ERROR("Command takes exactly 2 arguments");
1749 return ERROR_COMMAND_SYNTAX_ERROR
;
1753 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1755 if (!strcmp(CMD_ARGV
[0], "idcode")) {
1756 buf_set_u32(ir_idcode
, 0, 32, value
);
1758 } else if (!strcmp(CMD_ARGV
[0], "dtmcs")) {
1759 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
1761 } else if (!strcmp(CMD_ARGV
[0], "dmi")) {
1762 buf_set_u32(ir_dbus
, 0, 32, value
);
1769 static const struct command_registration riscv_exec_command_handlers
[] = {
1771 .name
= "test_compliance",
1772 .handler
= riscv_test_compliance
,
1773 .mode
= COMMAND_EXEC
,
1774 .usage
= "riscv test_compliance",
1775 .help
= "Runs a basic compliance test suite against the RISC-V Debug Spec."
1778 .name
= "set_command_timeout_sec",
1779 .handler
= riscv_set_command_timeout_sec
,
1780 .mode
= COMMAND_ANY
,
1781 .usage
= "riscv set_command_timeout_sec [sec]",
1782 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
1785 .name
= "set_reset_timeout_sec",
1786 .handler
= riscv_set_reset_timeout_sec
,
1787 .mode
= COMMAND_ANY
,
1788 .usage
= "riscv set_reset_timeout_sec [sec]",
1789 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
1792 .name
= "set_prefer_sba",
1793 .handler
= riscv_set_prefer_sba
,
1794 .mode
= COMMAND_ANY
,
1795 .usage
= "riscv set_prefer_sba on|off",
1796 .help
= "When on, prefer to use System Bus Access to access memory. "
1797 "When off, prefer to use the Program Buffer to access memory."
1800 .name
= "expose_csrs",
1801 .handler
= riscv_set_expose_csrs
,
1802 .mode
= COMMAND_ANY
,
1803 .usage
= "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1804 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
1805 "addition to the standard ones. This must be executed before "
1809 .name
= "expose_custom",
1810 .handler
= riscv_set_expose_custom
,
1811 .mode
= COMMAND_ANY
,
1812 .usage
= "riscv expose_custom n0[-m0][,n1[-m1]]...",
1813 .help
= "Configure a list of inclusive ranges for custom registers to "
1814 "expose. custom0 is accessed as abstract register number 0xc000, "
1815 "etc. This must be executed before `init`."
1818 .name
= "authdata_read",
1819 .handler
= riscv_authdata_read
,
1820 .mode
= COMMAND_ANY
,
1821 .usage
= "riscv authdata_read",
1822 .help
= "Return the 32-bit value read from authdata."
1825 .name
= "authdata_write",
1826 .handler
= riscv_authdata_write
,
1827 .mode
= COMMAND_ANY
,
1828 .usage
= "riscv authdata_write value",
1829 .help
= "Write the 32-bit value to authdata."
1833 .handler
= riscv_dmi_read
,
1834 .mode
= COMMAND_ANY
,
1835 .usage
= "riscv dmi_read address",
1836 .help
= "Perform a 32-bit DMI read at address, returning the value."
1839 .name
= "dmi_write",
1840 .handler
= riscv_dmi_write
,
1841 .mode
= COMMAND_ANY
,
1842 .usage
= "riscv dmi_write address value",
1843 .help
= "Perform a 32-bit DMI write of value at address."
1846 .name
= "test_sba_config_reg",
1847 .handler
= riscv_test_sba_config_reg
,
1848 .mode
= COMMAND_ANY
,
1849 .usage
= "riscv test_sba_config_reg legal_address num_words "
1850 "illegal_address run_sbbusyerror_test[on/off]",
1851 .help
= "Perform a series of tests on the SBCS register. "
1852 "Inputs are a legal, 128-byte aligned address and a number of words to "
1853 "read/write starting at that address (i.e., address range [legal address, "
1854 "legal_address+word_size*num_words) must be legally readable/writable), "
1855 "an illegal, 128-byte aligned address for error flag/handling cases, "
1856 "and whether sbbusyerror test should be run."
1859 .name
= "reset_delays",
1860 .handler
= riscv_reset_delays
,
1861 .mode
= COMMAND_ANY
,
1862 .usage
= "reset_delays [wait]",
1863 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
1864 "between scans to avoid encountering the target being busy. This "
1865 "command resets those learned values after `wait` scans. It's only "
1866 "useful for testing OpenOCD itself."
1870 .handler
= riscv_set_ir
,
1871 .mode
= COMMAND_ANY
,
1872 .usage
= "riscv set_ir_idcode [idcode|dtmcs|dmi] value",
1873 .help
= "Set IR value for specified JTAG register."
1875 COMMAND_REGISTRATION_DONE
1879 * To be noted that RISC-V targets use the same semihosting commands as
1882 * The main reason is compatibility with existing tools. For example the
1883 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1884 * configure semihosting, which generate commands like `arm semihosting
1886 * A secondary reason is the fact that the protocol used is exactly the
1887 * one specified by ARM. If RISC-V will ever define its own semihosting
1888 * protocol, then a command like `riscv semihosting enable` will make
1889 * sense, but for now all semihosting commands are prefixed with `arm`.
1891 extern const struct command_registration semihosting_common_handlers
[];
1893 const struct command_registration riscv_command_handlers
[] = {
1896 .mode
= COMMAND_ANY
,
1897 .help
= "RISC-V Command Group",
1899 .chain
= riscv_exec_command_handlers
1903 .mode
= COMMAND_ANY
,
1904 .help
= "ARM Command Group",
1906 .chain
= semihosting_common_handlers
1908 COMMAND_REGISTRATION_DONE
1911 unsigned riscv_address_bits(struct target
*target
)
1913 return riscv_xlen(target
);
1916 struct target_type riscv_target
= {
1919 .init_target
= riscv_init_target
,
1920 .deinit_target
= riscv_deinit_target
,
1921 .examine
= riscv_examine
,
1923 /* poll current target status */
1924 .poll
= old_or_new_riscv_poll
,
1926 .halt
= old_or_new_riscv_halt
,
1927 .resume
= old_or_new_riscv_resume
,
1928 .step
= old_or_new_riscv_step
,
1930 .assert_reset
= riscv_assert_reset
,
1931 .deassert_reset
= riscv_deassert_reset
,
1933 .read_memory
= riscv_read_memory
,
1934 .write_memory
= riscv_write_memory
,
1936 .checksum_memory
= riscv_checksum_memory
,
1938 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
1940 .add_breakpoint
= riscv_add_breakpoint
,
1941 .remove_breakpoint
= riscv_remove_breakpoint
,
1943 .add_watchpoint
= riscv_add_watchpoint
,
1944 .remove_watchpoint
= riscv_remove_watchpoint
,
1945 .hit_watchpoint
= riscv_hit_watchpoint
,
1947 .arch_state
= riscv_arch_state
,
1949 .run_algorithm
= riscv_run_algorithm
,
1951 .commands
= riscv_command_handlers
,
1953 .address_bits
= riscv_address_bits
1956 /*** RISC-V Interface ***/
1958 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
1960 memset(r
, 0, sizeof(*r
));
1962 r
->registers_initialized
= false;
1963 r
->current_hartid
= target
->coreid
;
1965 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
1967 for (size_t h
= 0; h
< RISCV_MAX_HARTS
; ++h
) {
1970 for (size_t e
= 0; e
< RISCV_MAX_REGISTERS
; ++e
)
1971 r
->valid_saved_registers
[h
][e
] = false;
1975 int riscv_halt_all_harts(struct target
*target
)
1977 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1978 if (!riscv_hart_enabled(target
, i
))
1981 riscv_halt_one_hart(target
, i
);
1984 riscv_invalidate_register_cache(target
);
1989 int riscv_halt_one_hart(struct target
*target
, int hartid
)
1992 LOG_DEBUG("halting hart %d", hartid
);
1993 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1995 if (riscv_is_halted(target
)) {
1996 LOG_DEBUG(" hart %d requested halt, but was already halted", hartid
);
2000 int result
= r
->halt_current_hart(target
);
2001 register_cache_invalidate(target
->reg_cache
);
2005 int riscv_resume_all_harts(struct target
*target
)
2007 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2008 if (!riscv_hart_enabled(target
, i
))
2011 riscv_resume_one_hart(target
, i
);
2014 riscv_invalidate_register_cache(target
);
2018 int riscv_resume_one_hart(struct target
*target
, int hartid
)
2021 LOG_DEBUG("resuming hart %d", hartid
);
2022 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2024 if (!riscv_is_halted(target
)) {
2025 LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid
);
2029 r
->on_resume(target
);
2030 return r
->resume_current_hart(target
);
2033 int riscv_step_rtos_hart(struct target
*target
)
2036 int hartid
= r
->current_hartid
;
2037 if (riscv_rtos_enabled(target
)) {
2038 hartid
= r
->rtos_hartid
;
2040 LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2044 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2046 LOG_DEBUG("stepping hart %d", hartid
);
2048 if (!riscv_is_halted(target
)) {
2049 LOG_ERROR("Hart isn't halted before single step!");
2052 riscv_invalidate_register_cache(target
);
2054 if (r
->step_current_hart(target
) != ERROR_OK
)
2056 riscv_invalidate_register_cache(target
);
2058 if (!riscv_is_halted(target
)) {
2059 LOG_ERROR("Hart was not halted after single step!");
2065 bool riscv_supports_extension(struct target
*target
, int hartid
, char letter
)
2069 if (letter
>= 'a' && letter
<= 'z')
2071 else if (letter
>= 'A' && letter
<= 'Z')
2075 return r
->misa
[hartid
] & (1 << num
);
2078 int riscv_xlen(const struct target
*target
)
2080 return riscv_xlen_of_hart(target
, riscv_current_hartid(target
));
2083 int riscv_xlen_of_hart(const struct target
*target
, int hartid
)
2086 assert(r
->xlen
[hartid
] != -1);
2087 return r
->xlen
[hartid
];
2090 extern struct rtos_type riscv_rtos
;
2091 bool riscv_rtos_enabled(const struct target
*target
)
2096 int riscv_set_current_hartid(struct target
*target
, int hartid
)
2099 if (!r
->select_current_hart
)
2102 int previous_hartid
= riscv_current_hartid(target
);
2103 r
->current_hartid
= hartid
;
2104 assert(riscv_hart_enabled(target
, hartid
));
2105 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
2106 if (r
->select_current_hart(target
) != ERROR_OK
)
2109 /* This might get called during init, in which case we shouldn't be
2110 * setting up the register cache. */
2111 if (target_was_examined(target
) && riscv_rtos_enabled(target
))
2112 riscv_invalidate_register_cache(target
);
2117 void riscv_invalidate_register_cache(struct target
*target
)
2121 LOG_DEBUG("[%d]", target
->coreid
);
2122 register_cache_invalidate(target
->reg_cache
);
2123 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
2124 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
2128 r
->registers_initialized
= true;
2131 int riscv_current_hartid(const struct target
*target
)
2134 return r
->current_hartid
;
2137 void riscv_set_all_rtos_harts(struct target
*target
)
2140 r
->rtos_hartid
= -1;
2143 void riscv_set_rtos_hartid(struct target
*target
, int hartid
)
2145 LOG_DEBUG("setting RTOS hartid %d", hartid
);
2147 r
->rtos_hartid
= hartid
;
2150 int riscv_count_harts(struct target
*target
)
2157 return r
->hart_count
;
2160 bool riscv_has_register(struct target
*target
, int hartid
, int regid
)
2166 * This function is called when the debug user wants to change the value of a
2167 * register. The new value may be cached, and may not be written until the hart
2169 int riscv_set_register(struct target
*target
, enum gdb_regno r
, riscv_reg_t v
)
2171 return riscv_set_register_on_hart(target
, riscv_current_hartid(target
), r
, v
);
2174 int riscv_set_register_on_hart(struct target
*target
, int hartid
,
2175 enum gdb_regno regid
, uint64_t value
)
2178 LOG_DEBUG("{%d} %s <- %" PRIx64
, hartid
, gdb_regno_name(regid
), value
);
2179 assert(r
->set_register
);
2180 return r
->set_register(target
, hartid
, regid
, value
);
2183 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
2186 return riscv_get_register_on_hart(target
, value
,
2187 riscv_current_hartid(target
), r
);
2190 int riscv_get_register_on_hart(struct target
*target
, riscv_reg_t
*value
,
2191 int hartid
, enum gdb_regno regid
)
2195 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
2197 if (reg
&& reg
->valid
&& hartid
== riscv_current_hartid(target
)) {
2198 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
2202 int result
= r
->get_register(target
, value
, hartid
, regid
);
2204 LOG_DEBUG("{%d} %s: %" PRIx64
, hartid
, gdb_regno_name(regid
), *value
);
2208 bool riscv_is_halted(struct target
*target
)
2211 assert(r
->is_halted
);
2212 return r
->is_halted(target
);
2215 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
2218 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2219 return RISCV_HALT_ERROR
;
2220 if (!riscv_is_halted(target
)) {
2221 LOG_ERROR("Hart is not halted!");
2222 return RISCV_HALT_UNKNOWN
;
2224 return r
->halt_reason(target
);
2227 size_t riscv_debug_buffer_size(struct target
*target
)
2230 return r
->debug_buffer_size
[riscv_current_hartid(target
)];
2233 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
2236 r
->write_debug_buffer(target
, index
, insn
);
2240 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
2243 return r
->read_debug_buffer(target
, index
);
2246 int riscv_execute_debug_buffer(struct target
*target
)
2249 return r
->execute_debug_buffer(target
);
2252 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
2255 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
2258 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
2261 r
->fill_dmi_read_u64(target
, buf
, a
);
2264 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
2267 r
->fill_dmi_nop_u64(target
, buf
);
2270 int riscv_dmi_write_u64_bits(struct target
*target
)
2273 return r
->dmi_write_u64_bits(target
);
2276 bool riscv_hart_enabled(struct target
*target
, int hartid
)
2278 /* FIXME: Add a hart mask to the RTOS. */
2279 if (riscv_rtos_enabled(target
))
2280 return hartid
< riscv_count_harts(target
);
2282 return hartid
== target
->coreid
;
2286 * Count triggers, and initialize trigger_count for each hart.
2287 * trigger_count is initialized even if this function fails to discover
2289 * Disable any hardware triggers that have dmode set. We can't have set them
2290 * ourselves. Maybe they're left over from some killed debug session.
2292 int riscv_enumerate_triggers(struct target
*target
)
2296 if (r
->triggers_enumerated
)
2299 r
->triggers_enumerated
= true; /* At the very least we tried. */
2301 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
2302 if (!riscv_hart_enabled(target
, hartid
))
2305 riscv_reg_t tselect
;
2306 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
,
2308 if (result
!= ERROR_OK
)
2311 for (unsigned t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
2312 r
->trigger_count
[hartid
] = t
;
2314 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, t
);
2315 uint64_t tselect_rb
;
2316 result
= riscv_get_register_on_hart(target
, &tselect_rb
, hartid
,
2318 if (result
!= ERROR_OK
)
2320 /* Mask off the top bit, which is used as tdrmode in old
2321 * implementations. */
2322 tselect_rb
&= ~(1ULL << (riscv_xlen(target
)-1));
2323 if (tselect_rb
!= t
)
2326 result
= riscv_get_register_on_hart(target
, &tdata1
, hartid
,
2328 if (result
!= ERROR_OK
)
2331 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
2334 /* On these older cores we don't support software using
2336 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2339 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
2340 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
2345 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
2347 LOG_INFO("[%d] Found %d triggers", hartid
, r
->trigger_count
[hartid
]);
2353 const char *gdb_regno_name(enum gdb_regno regno
)
2355 static char buf
[32];
2358 case GDB_REGNO_ZERO
:
2366 case GDB_REGNO_FPR0
:
2368 case GDB_REGNO_FPR31
:
2370 case GDB_REGNO_CSR0
:
2372 case GDB_REGNO_TSELECT
:
2374 case GDB_REGNO_TDATA1
:
2376 case GDB_REGNO_TDATA2
:
2378 case GDB_REGNO_MISA
:
2382 case GDB_REGNO_DCSR
:
2384 case GDB_REGNO_DSCRATCH
:
2386 case GDB_REGNO_MSTATUS
:
2388 case GDB_REGNO_PRIV
:
2391 if (regno
<= GDB_REGNO_XPR31
)
2392 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
2393 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
2394 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
2395 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
2396 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
2398 sprintf(buf
, "gdb_regno_%d", regno
);
2403 static int register_get(struct reg
*reg
)
2405 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2406 struct target
*target
= reg_info
->target
;
2408 int result
= riscv_get_register(target
, &value
, reg
->number
);
2409 if (result
!= ERROR_OK
)
2411 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
2412 /* CSRs (and possibly other extension) registers may change value at any
2414 if (reg
->number
<= GDB_REGNO_XPR31
||
2415 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2416 reg
->number
== GDB_REGNO_PC
)
2418 LOG_DEBUG("[%d]{%d} read 0x%" PRIx64
" from %s (valid=%d)",
2419 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2424 static int register_set(struct reg
*reg
, uint8_t *buf
)
2426 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
2427 struct target
*target
= reg_info
->target
;
2429 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
2431 LOG_DEBUG("[%d]{%d} write 0x%" PRIx64
" to %s (valid=%d)",
2432 target
->coreid
, riscv_current_hartid(target
), value
, reg
->name
,
2434 struct reg
*r
= &target
->reg_cache
->reg_list
[reg
->number
];
2435 /* CSRs (and possibly other extension) registers may change value at any
2437 if (reg
->number
<= GDB_REGNO_XPR31
||
2438 (reg
->number
>= GDB_REGNO_FPR0
&& reg
->number
<= GDB_REGNO_FPR31
) ||
2439 reg
->number
== GDB_REGNO_PC
)
2441 memcpy(r
->value
, buf
, (r
->size
+ 7) / 8);
2443 riscv_set_register(target
, reg
->number
, value
);
2447 static struct reg_arch_type riscv_reg_arch_type
= {
2448 .get
= register_get
,
2457 static int cmp_csr_info(const void *p1
, const void *p2
)
2459 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
2462 int riscv_init_registers(struct target
*target
)
2466 riscv_free_registers(target
);
2468 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
2469 target
->reg_cache
->name
= "RISC-V Registers";
2470 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
2472 if (expose_custom
) {
2473 for (unsigned i
= 0; expose_custom
[i
].low
<= expose_custom
[i
].high
; i
++) {
2474 for (unsigned number
= expose_custom
[i
].low
;
2475 number
<= expose_custom
[i
].high
;
2477 target
->reg_cache
->num_regs
++;
2481 LOG_DEBUG("create register cache for %d registers",
2482 target
->reg_cache
->num_regs
);
2484 target
->reg_cache
->reg_list
=
2485 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
2487 const unsigned int max_reg_name_len
= 12;
2488 free(info
->reg_names
);
2490 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
2491 char *reg_name
= info
->reg_names
;
2493 static struct reg_feature feature_cpu
= {
2494 .name
= "org.gnu.gdb.riscv.cpu"
2496 static struct reg_feature feature_fpu
= {
2497 .name
= "org.gnu.gdb.riscv.fpu"
2499 static struct reg_feature feature_csr
= {
2500 .name
= "org.gnu.gdb.riscv.csr"
2502 static struct reg_feature feature_virtual
= {
2503 .name
= "org.gnu.gdb.riscv.virtual"
2505 static struct reg_feature feature_custom
= {
2506 .name
= "org.gnu.gdb.riscv.custom"
2509 static struct reg_data_type type_ieee_single
= {
2510 .type
= REG_TYPE_IEEE_SINGLE
,
2513 static struct reg_data_type type_ieee_double
= {
2514 .type
= REG_TYPE_IEEE_DOUBLE
,
2517 struct csr_info csr_info
[] = {
2518 #define DECLARE_CSR(name, number) { number, #name },
2519 #include "encoding.h"
2522 /* encoding.h does not contain the registers in sorted order. */
2523 qsort(csr_info
, DIM(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
2524 unsigned csr_info_index
= 0;
2526 unsigned custom_range_index
= 0;
2527 int custom_within_range
= 0;
2529 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
2530 shared_reg_info
->target
= target
;
2532 /* When gdb requests register N, gdb_get_register_packet() assumes that this
2533 * is register at index N in reg_list. So if there are certain registers
2534 * that don't exist, we need to leave holes in the list (or renumber, but
2535 * it would be nice not to have yet another set of numbers to translate
2537 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
2538 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
2542 r
->type
= &riscv_reg_arch_type
;
2543 r
->arch_info
= shared_reg_info
;
2545 r
->size
= riscv_xlen(target
);
2546 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2547 * target is in theory allowed to change XLEN on us. But I expect a lot
2548 * of other things to break in that case as well. */
2549 if (number
<= GDB_REGNO_XPR31
) {
2550 r
->caller_save
= true;
2552 case GDB_REGNO_ZERO
:
2649 r
->group
= "general";
2650 r
->feature
= &feature_cpu
;
2651 } else if (number
== GDB_REGNO_PC
) {
2652 r
->caller_save
= true;
2653 sprintf(reg_name
, "pc");
2654 r
->group
= "general";
2655 r
->feature
= &feature_cpu
;
2656 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
2657 r
->caller_save
= true;
2658 if (riscv_supports_extension(target
, riscv_current_hartid(target
),
2660 r
->reg_data_type
= &type_ieee_double
;
2662 } else if (riscv_supports_extension(target
,
2663 riscv_current_hartid(target
), 'F')) {
2664 r
->reg_data_type
= &type_ieee_single
;
2748 case GDB_REGNO_FS10
:
2751 case GDB_REGNO_FS11
:
2760 case GDB_REGNO_FT10
:
2763 case GDB_REGNO_FT11
:
2768 r
->feature
= &feature_fpu
;
2769 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
2771 r
->feature
= &feature_csr
;
2772 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
2774 while (csr_info
[csr_info_index
].number
< csr_number
&&
2775 csr_info_index
< DIM(csr_info
) - 1) {
2778 if (csr_info
[csr_info_index
].number
== csr_number
) {
2779 r
->name
= csr_info
[csr_info_index
].name
;
2781 sprintf(reg_name
, "csr%d", csr_number
);
2782 /* Assume unnamed registers don't exist, unless we have some
2783 * configuration that tells us otherwise. That's important
2784 * because eg. Eclipse crashes if a target has too many
2785 * registers, and apparently has no way of only showing a
2786 * subset of registers in any case. */
2790 switch (csr_number
) {
2794 r
->exist
= riscv_supports_extension(target
,
2795 riscv_current_hartid(target
), 'F');
2797 r
->feature
= &feature_fpu
;
2803 case CSR_SCOUNTEREN
:
2809 r
->exist
= riscv_supports_extension(target
,
2810 riscv_current_hartid(target
), 'S');
2814 /* "In systems with only M-mode, or with both M-mode and
2815 * U-mode but without U-mode trap support, the medeleg and
2816 * mideleg registers should not exist." */
2817 r
->exist
= riscv_supports_extension(target
, riscv_current_hartid(target
), 'S') ||
2818 riscv_supports_extension(target
, riscv_current_hartid(target
), 'N');
2824 case CSR_HPMCOUNTER3H
:
2825 case CSR_HPMCOUNTER4H
:
2826 case CSR_HPMCOUNTER5H
:
2827 case CSR_HPMCOUNTER6H
:
2828 case CSR_HPMCOUNTER7H
:
2829 case CSR_HPMCOUNTER8H
:
2830 case CSR_HPMCOUNTER9H
:
2831 case CSR_HPMCOUNTER10H
:
2832 case CSR_HPMCOUNTER11H
:
2833 case CSR_HPMCOUNTER12H
:
2834 case CSR_HPMCOUNTER13H
:
2835 case CSR_HPMCOUNTER14H
:
2836 case CSR_HPMCOUNTER15H
:
2837 case CSR_HPMCOUNTER16H
:
2838 case CSR_HPMCOUNTER17H
:
2839 case CSR_HPMCOUNTER18H
:
2840 case CSR_HPMCOUNTER19H
:
2841 case CSR_HPMCOUNTER20H
:
2842 case CSR_HPMCOUNTER21H
:
2843 case CSR_HPMCOUNTER22H
:
2844 case CSR_HPMCOUNTER23H
:
2845 case CSR_HPMCOUNTER24H
:
2846 case CSR_HPMCOUNTER25H
:
2847 case CSR_HPMCOUNTER26H
:
2848 case CSR_HPMCOUNTER27H
:
2849 case CSR_HPMCOUNTER28H
:
2850 case CSR_HPMCOUNTER29H
:
2851 case CSR_HPMCOUNTER30H
:
2852 case CSR_HPMCOUNTER31H
:
2855 case CSR_MHPMCOUNTER3H
:
2856 case CSR_MHPMCOUNTER4H
:
2857 case CSR_MHPMCOUNTER5H
:
2858 case CSR_MHPMCOUNTER6H
:
2859 case CSR_MHPMCOUNTER7H
:
2860 case CSR_MHPMCOUNTER8H
:
2861 case CSR_MHPMCOUNTER9H
:
2862 case CSR_MHPMCOUNTER10H
:
2863 case CSR_MHPMCOUNTER11H
:
2864 case CSR_MHPMCOUNTER12H
:
2865 case CSR_MHPMCOUNTER13H
:
2866 case CSR_MHPMCOUNTER14H
:
2867 case CSR_MHPMCOUNTER15H
:
2868 case CSR_MHPMCOUNTER16H
:
2869 case CSR_MHPMCOUNTER17H
:
2870 case CSR_MHPMCOUNTER18H
:
2871 case CSR_MHPMCOUNTER19H
:
2872 case CSR_MHPMCOUNTER20H
:
2873 case CSR_MHPMCOUNTER21H
:
2874 case CSR_MHPMCOUNTER22H
:
2875 case CSR_MHPMCOUNTER23H
:
2876 case CSR_MHPMCOUNTER24H
:
2877 case CSR_MHPMCOUNTER25H
:
2878 case CSR_MHPMCOUNTER26H
:
2879 case CSR_MHPMCOUNTER27H
:
2880 case CSR_MHPMCOUNTER28H
:
2881 case CSR_MHPMCOUNTER29H
:
2882 case CSR_MHPMCOUNTER30H
:
2883 case CSR_MHPMCOUNTER31H
:
2884 r
->exist
= riscv_xlen(target
) == 32;
2888 if (!r
->exist
&& expose_csr
) {
2889 for (unsigned i
= 0; expose_csr
[i
].low
<= expose_csr
[i
].high
; i
++) {
2890 if (csr_number
>= expose_csr
[i
].low
&& csr_number
<= expose_csr
[i
].high
) {
2891 LOG_INFO("Exposing additional CSR %d", csr_number
);
2898 } else if (number
== GDB_REGNO_PRIV
) {
2899 sprintf(reg_name
, "priv");
2900 r
->group
= "general";
2901 r
->feature
= &feature_virtual
;
2905 /* Custom registers. */
2906 assert(expose_custom
);
2908 range_t
*range
= &expose_custom
[custom_range_index
];
2909 assert(range
->low
<= range
->high
);
2910 unsigned custom_number
= range
->low
+ custom_within_range
;
2912 r
->group
= "custom";
2913 r
->feature
= &feature_custom
;
2914 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
2915 assert(r
->arch_info
);
2916 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
2917 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
2918 sprintf(reg_name
, "custom%d", custom_number
);
2920 custom_within_range
++;
2921 if (custom_within_range
> range
->high
- range
->low
) {
2922 custom_within_range
= 0;
2923 custom_range_index
++;
2929 reg_name
+= strlen(reg_name
) + 1;
2930 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
2932 r
->value
= &info
->reg_cache_values
[number
];
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|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)