Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / riscv / riscv-011.c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /*
4 * Support for RISC-V, debug version 0.11. This was never an officially adopted
5 * spec, but SiFive made some silicon that uses it.
6 */
7
8 #include <assert.h>
9 #include <stdlib.h>
10 #include <time.h>
11
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15
16 #include "target/target.h"
17 #include "target/algorithm.h"
18 #include "target/target_type.h"
19 #include "log.h"
20 #include "jtag/jtag.h"
21 #include "target/register.h"
22 #include "target/breakpoints.h"
23 #include "helper/time_support.h"
24 #include "riscv.h"
25 #include "asm.h"
26 #include "gdb_regs.h"
27
28 /**
29 * Since almost everything can be accomplish by scanning the dbus register, all
30 * functions here assume dbus is already selected. The exception are functions
31 * called directly by OpenOCD, which can't assume anything about what's
32 * currently in IR. They should set IR to dbus explicitly.
33 */
34
35 /**
36 * Code structure
37 *
38 * At the bottom of the stack are the OpenOCD JTAG functions:
39 * jtag_add_[id]r_scan
40 * jtag_execute_query
41 * jtag_add_runtest
42 *
43 * There are a few functions to just instantly shift a register and get its
44 * value:
45 * dtmcontrol_scan
46 * idcode_scan
47 * dbus_scan
48 *
49 * Because doing one scan and waiting for the result is slow, most functions
50 * batch up a bunch of dbus writes and then execute them all at once. They use
51 * the scans "class" for this:
52 * scans_new
53 * scans_delete
54 * scans_execute
55 * scans_add_...
56 * Usually you new(), call a bunch of add functions, then execute() and look
57 * at the results by calling scans_get...()
58 *
59 * Optimized functions will directly use the scans class above, but slightly
60 * lazier code will use the cache functions that in turn use the scans
61 * functions:
62 * cache_get...
63 * cache_set...
64 * cache_write
65 * cache_set... update a local structure, which is then synced to the target
66 * with cache_write(). Only Debug RAM words that are actually changed are sent
67 * to the target. Afterwards use cache_get... to read results.
68 */
69
70 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
71 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
72
73 #define DIM(x) (sizeof(x)/sizeof(*x))
74
75 /* Constants for legacy SiFive hardware breakpoints. */
76 #define CSR_BPCONTROL_X (1<<0)
77 #define CSR_BPCONTROL_W (1<<1)
78 #define CSR_BPCONTROL_R (1<<2)
79 #define CSR_BPCONTROL_U (1<<3)
80 #define CSR_BPCONTROL_S (1<<4)
81 #define CSR_BPCONTROL_H (1<<5)
82 #define CSR_BPCONTROL_M (1<<6)
83 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
84 #define CSR_BPCONTROL_BPACTION (0xff<<11)
85
86 #define DEBUG_ROM_START 0x800
87 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
88 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
89 #define DEBUG_RAM_START 0x400
90
91 #define SETHALTNOT 0x10c
92
93 /*** JTAG registers. ***/
94
95 #define DTMCONTROL 0x10
96 #define DTMCONTROL_DBUS_RESET (1<<16)
97 #define DTMCONTROL_IDLE (7<<10)
98 #define DTMCONTROL_ADDRBITS (0xf<<4)
99 #define DTMCONTROL_VERSION (0xf)
100
101 #define DBUS 0x11
102 #define DBUS_OP_START 0
103 #define DBUS_OP_SIZE 2
104 typedef enum {
105 DBUS_OP_NOP = 0,
106 DBUS_OP_READ = 1,
107 DBUS_OP_WRITE = 2
108 } dbus_op_t;
109 typedef enum {
110 DBUS_STATUS_SUCCESS = 0,
111 DBUS_STATUS_FAILED = 2,
112 DBUS_STATUS_BUSY = 3
113 } dbus_status_t;
114 #define DBUS_DATA_START 2
115 #define DBUS_DATA_SIZE 34
116 #define DBUS_ADDRESS_START 36
117
118 typedef enum {
119 RE_OK,
120 RE_FAIL,
121 RE_AGAIN
122 } riscv_error_t;
123
124 typedef enum slot {
125 SLOT0,
126 SLOT1,
127 SLOT_LAST,
128 } slot_t;
129
130 /*** Debug Bus registers. ***/
131
132 #define DMCONTROL 0x10
133 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
134 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
135 #define DMCONTROL_BUSERROR (7<<19)
136 #define DMCONTROL_SERIAL (3<<16)
137 #define DMCONTROL_AUTOINCREMENT (1<<15)
138 #define DMCONTROL_ACCESS (7<<12)
139 #define DMCONTROL_HARTID (0x3ff<<2)
140 #define DMCONTROL_NDRESET (1<<1)
141 #define DMCONTROL_FULLRESET 1
142
143 #define DMINFO 0x11
144 #define DMINFO_ABUSSIZE (0x7fU<<25)
145 #define DMINFO_SERIALCOUNT (0xf<<21)
146 #define DMINFO_ACCESS128 (1<<20)
147 #define DMINFO_ACCESS64 (1<<19)
148 #define DMINFO_ACCESS32 (1<<18)
149 #define DMINFO_ACCESS16 (1<<17)
150 #define DMINFO_ACCESS8 (1<<16)
151 #define DMINFO_DRAMSIZE (0x3f<<10)
152 #define DMINFO_AUTHENTICATED (1<<5)
153 #define DMINFO_AUTHBUSY (1<<4)
154 #define DMINFO_AUTHTYPE (3<<2)
155 #define DMINFO_VERSION 3
156
157 /*** Info about the core being debugged. ***/
158
159 #define DBUS_ADDRESS_UNKNOWN 0xffff
160
161 #define DRAM_CACHE_SIZE 16
162
163 struct trigger {
164 uint64_t address;
165 uint32_t length;
166 uint64_t mask;
167 uint64_t value;
168 bool read, write, execute;
169 int unique_id;
170 };
171
172 struct memory_cache_line {
173 uint32_t data;
174 bool valid;
175 bool dirty;
176 };
177
178 typedef struct {
179 /* Number of address bits in the dbus register. */
180 uint8_t addrbits;
181 /* Number of words in Debug RAM. */
182 unsigned int dramsize;
183 uint64_t dcsr;
184 uint64_t dpc;
185 uint64_t tselect;
186 bool tselect_dirty;
187 /* The value that mstatus actually has on the target right now. This is not
188 * the value we present to the user. That one may be stored in the
189 * reg_cache. */
190 uint64_t mstatus_actual;
191
192 struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
193
194 /* Number of run-test/idle cycles the target requests we do after each dbus
195 * access. */
196 unsigned int dtmcontrol_idle;
197
198 /* This value is incremented every time a dbus access comes back as "busy".
199 * It's used to determine how many run-test/idle cycles to feed the target
200 * in between accesses. */
201 unsigned int dbus_busy_delay;
202
203 /* This value is incremented every time we read the debug interrupt as
204 * high. It's used to add extra run-test/idle cycles after setting debug
205 * interrupt high, so ideally we never have to perform a whole extra scan
206 * before the interrupt is cleared. */
207 unsigned int interrupt_high_delay;
208
209 bool never_halted;
210 } riscv011_info_t;
211
212 typedef struct {
213 bool haltnot;
214 bool interrupt;
215 } bits_t;
216
217 /*** Necessary prototypes. ***/
218
219 static int poll_target(struct target *target, bool announce);
220 static int riscv011_poll(struct target *target);
221 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
222 int regid);
223
224 /*** Utility functions. ***/
225
226 #define DEBUG_LENGTH 264
227
228 static riscv011_info_t *get_info(const struct target *target)
229 {
230 riscv_info_t *info = (riscv_info_t *) target->arch_info;
231 return (riscv011_info_t *) info->version_specific;
232 }
233
234 static unsigned int slot_offset(const struct target *target, slot_t slot)
235 {
236 riscv011_info_t *info = get_info(target);
237 switch (riscv_xlen(target)) {
238 case 32:
239 switch (slot) {
240 case SLOT0: return 4;
241 case SLOT1: return 5;
242 case SLOT_LAST: return info->dramsize-1;
243 }
244 break;
245 case 64:
246 switch (slot) {
247 case SLOT0: return 4;
248 case SLOT1: return 6;
249 case SLOT_LAST: return info->dramsize-2;
250 }
251 }
252 LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
253 riscv_xlen(target), slot);
254 assert(0);
255 return 0; /* Silence -Werror=return-type */
256 }
257
258 static uint32_t load_slot(const struct target *target, unsigned int dest,
259 slot_t slot)
260 {
261 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
262 return load(target, dest, ZERO, offset);
263 }
264
265 static uint32_t store_slot(const struct target *target, unsigned int src,
266 slot_t slot)
267 {
268 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
269 return store(target, src, ZERO, offset);
270 }
271
272 static uint16_t dram_address(unsigned int index)
273 {
274 if (index < 0x10)
275 return index;
276 else
277 return 0x40 + index - 0x10;
278 }
279
280 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
281 {
282 struct scan_field field;
283 uint8_t in_value[4];
284 uint8_t out_value[4] = { 0 };
285
286 buf_set_u32(out_value, 0, 32, out);
287
288 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
289
290 field.num_bits = 32;
291 field.out_value = out_value;
292 field.in_value = in_value;
293 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
294
295 /* Always return to dbus. */
296 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
297
298 int retval = jtag_execute_queue();
299 if (retval != ERROR_OK) {
300 LOG_ERROR("failed jtag scan: %d", retval);
301 return retval;
302 }
303
304 uint32_t in = buf_get_u32(field.in_value, 0, 32);
305 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
306
307 return in;
308 }
309
310 static uint32_t idcode_scan(struct target *target)
311 {
312 struct scan_field field;
313 uint8_t in_value[4];
314
315 jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
316
317 field.num_bits = 32;
318 field.out_value = NULL;
319 field.in_value = in_value;
320 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
321
322 int retval = jtag_execute_queue();
323 if (retval != ERROR_OK) {
324 LOG_ERROR("failed jtag scan: %d", retval);
325 return retval;
326 }
327
328 /* Always return to dbus. */
329 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
330
331 uint32_t in = buf_get_u32(field.in_value, 0, 32);
332 LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
333
334 return in;
335 }
336
337 static void increase_dbus_busy_delay(struct target *target)
338 {
339 riscv011_info_t *info = get_info(target);
340 info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
341 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
342 info->dtmcontrol_idle, info->dbus_busy_delay,
343 info->interrupt_high_delay);
344
345 dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
346 }
347
348 static void increase_interrupt_high_delay(struct target *target)
349 {
350 riscv011_info_t *info = get_info(target);
351 info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
352 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
353 info->dtmcontrol_idle, info->dbus_busy_delay,
354 info->interrupt_high_delay);
355 }
356
357 static void add_dbus_scan(const struct target *target, struct scan_field *field,
358 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
359 uint16_t address, uint64_t data)
360 {
361 riscv011_info_t *info = get_info(target);
362 RISCV_INFO(r);
363
364 if (r->reset_delays_wait >= 0) {
365 r->reset_delays_wait--;
366 if (r->reset_delays_wait < 0) {
367 info->dbus_busy_delay = 0;
368 info->interrupt_high_delay = 0;
369 }
370 }
371
372 field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
373 field->in_value = in_value;
374 field->out_value = out_value;
375
376 buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
377 buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
378 buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
379
380 jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
381
382 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
383 if (data & DMCONTROL_INTERRUPT)
384 idle_count += info->interrupt_high_delay;
385
386 if (idle_count)
387 jtag_add_runtest(idle_count, TAP_IDLE);
388 }
389
390 static void dump_field(const struct scan_field *field)
391 {
392 static const char * const op_string[] = {"nop", "r", "w", "?"};
393 static const char * const status_string[] = {"+", "?", "F", "b"};
394
395 if (debug_level < LOG_LVL_DEBUG)
396 return;
397
398 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
399 unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
400 char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
401 char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
402 unsigned int out_data = out >> 2;
403 unsigned int out_address = out >> DBUS_ADDRESS_START;
404 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
405 unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
406 char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
407 char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
408 unsigned int in_data = in >> 2;
409 unsigned int in_address = in >> DBUS_ADDRESS_START;
410
411 log_printf_lf(LOG_LVL_DEBUG,
412 __FILE__, __LINE__, "scan",
413 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
414 field->num_bits,
415 op_string[out_op], out_interrupt, out_haltnot, out_data,
416 out_address,
417 status_string[in_op], in_interrupt, in_haltnot, in_data,
418 in_address);
419 }
420
421 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
422 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
423 {
424 riscv011_info_t *info = get_info(target);
425 uint8_t in[8] = {0};
426 uint8_t out[8] = {0};
427 struct scan_field field = {
428 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
429 .out_value = out,
430 .in_value = in
431 };
432
433 assert(info->addrbits != 0);
434
435 buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
436 buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
437 buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
438
439 /* Assume dbus is already selected. */
440 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
441
442 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
443
444 if (idle_count)
445 jtag_add_runtest(idle_count, TAP_IDLE);
446
447 int retval = jtag_execute_queue();
448 if (retval != ERROR_OK) {
449 LOG_ERROR("dbus_scan failed jtag scan");
450 return DBUS_STATUS_FAILED;
451 }
452
453 if (data_in)
454 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
455
456 if (address_in)
457 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
458
459 dump_field(&field);
460
461 return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
462 }
463
464 static uint64_t dbus_read(struct target *target, uint16_t address)
465 {
466 uint64_t value;
467 dbus_status_t status;
468 uint16_t address_in;
469
470 /* If the previous read/write was to the same address, we will get the read data
471 * from the previous access.
472 * While somewhat nonintuitive, this is an efficient way to get the data.
473 */
474
475 unsigned i = 0;
476 do {
477 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
478 if (status == DBUS_STATUS_BUSY)
479 increase_dbus_busy_delay(target);
480 if (status == DBUS_STATUS_FAILED) {
481 LOG_ERROR("dbus_read(0x%x) failed!", address);
482 return 0;
483 }
484 } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
485 i++ < 256);
486
487 if (status != DBUS_STATUS_SUCCESS)
488 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
489
490 return value;
491 }
492
493 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
494 {
495 dbus_status_t status = DBUS_STATUS_BUSY;
496 unsigned i = 0;
497 while (status == DBUS_STATUS_BUSY && i++ < 256) {
498 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
499 if (status == DBUS_STATUS_BUSY)
500 increase_dbus_busy_delay(target);
501 }
502 if (status != DBUS_STATUS_SUCCESS)
503 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
504 }
505
506 /*** scans "class" ***/
507
508 typedef struct {
509 /* Number of scans that space is reserved for. */
510 unsigned int scan_count;
511 /* Size reserved in memory for each scan, in bytes. */
512 unsigned int scan_size;
513 unsigned int next_scan;
514 uint8_t *in;
515 uint8_t *out;
516 struct scan_field *field;
517 const struct target *target;
518 } scans_t;
519
520 static scans_t *scans_new(struct target *target, unsigned int scan_count)
521 {
522 scans_t *scans = malloc(sizeof(scans_t));
523 if (!scans)
524 goto error0;
525 scans->scan_count = scan_count;
526 /* This code also gets called before xlen is detected. */
527 if (riscv_xlen(target))
528 scans->scan_size = 2 + riscv_xlen(target) / 8;
529 else
530 scans->scan_size = 2 + 128 / 8;
531 scans->next_scan = 0;
532 scans->in = calloc(scans->scan_size, scans->scan_count);
533 if (!scans->in)
534 goto error1;
535 scans->out = calloc(scans->scan_size, scans->scan_count);
536 if (!scans->out)
537 goto error2;
538 scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
539 if (!scans->field)
540 goto error3;
541 scans->target = target;
542 return scans;
543
544 error3:
545 free(scans->out);
546 error2:
547 free(scans->in);
548 error1:
549 free(scans);
550 error0:
551 return NULL;
552 }
553
554 static scans_t *scans_delete(scans_t *scans)
555 {
556 assert(scans);
557 free(scans->field);
558 free(scans->out);
559 free(scans->in);
560 free(scans);
561 return NULL;
562 }
563
564 static void scans_reset(scans_t *scans)
565 {
566 scans->next_scan = 0;
567 }
568
569 static void scans_dump(scans_t *scans)
570 {
571 for (unsigned int i = 0; i < scans->next_scan; i++)
572 dump_field(&scans->field[i]);
573 }
574
575 static int scans_execute(scans_t *scans)
576 {
577 int retval = jtag_execute_queue();
578 if (retval != ERROR_OK) {
579 LOG_ERROR("failed jtag scan: %d", retval);
580 return retval;
581 }
582
583 scans_dump(scans);
584
585 return ERROR_OK;
586 }
587
588 /** Add a 32-bit dbus write to the scans structure. */
589 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
590 bool set_interrupt)
591 {
592 const unsigned int i = scans->next_scan;
593 int data_offset = scans->scan_size * i;
594 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
595 scans->in + data_offset, DBUS_OP_WRITE, address,
596 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
597 scans->next_scan++;
598 assert(scans->next_scan <= scans->scan_count);
599 }
600
601 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
602 * debug RAM. */
603 static void scans_add_write_jump(scans_t *scans, uint16_t address,
604 bool set_interrupt)
605 {
606 scans_add_write32(scans, address,
607 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
608 set_interrupt);
609 }
610
611 /** Add a 32-bit dbus write for an instruction that loads from the indicated
612 * slot. */
613 static void scans_add_write_load(scans_t *scans, uint16_t address,
614 unsigned int reg, slot_t slot, bool set_interrupt)
615 {
616 scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
617 set_interrupt);
618 }
619
620 /** Add a 32-bit dbus write for an instruction that stores to the indicated
621 * slot. */
622 static void scans_add_write_store(scans_t *scans, uint16_t address,
623 unsigned int reg, slot_t slot, bool set_interrupt)
624 {
625 scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
626 set_interrupt);
627 }
628
629 /** Add a 32-bit dbus read. */
630 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
631 {
632 assert(scans->next_scan < scans->scan_count);
633 const unsigned int i = scans->next_scan;
634 int data_offset = scans->scan_size * i;
635 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
636 scans->in + data_offset, DBUS_OP_READ, address,
637 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
638 scans->next_scan++;
639 }
640
641 /** Add one or more scans to read the indicated slot. */
642 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
643 {
644 const struct target *target = scans->target;
645 switch (riscv_xlen(target)) {
646 case 32:
647 scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
648 break;
649 case 64:
650 scans_add_read32(scans, slot_offset(target, slot), false);
651 scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
652 break;
653 }
654 }
655
656 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
657 unsigned first, unsigned num)
658 {
659 return buf_get_u32(scans->in + scans->scan_size * index, first, num);
660 }
661
662 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
663 unsigned first, unsigned num)
664 {
665 return buf_get_u64(scans->in + scans->scan_size * index, first, num);
666 }
667
668 /*** end of scans class ***/
669
670 static uint32_t dram_read32(struct target *target, unsigned int index)
671 {
672 uint16_t address = dram_address(index);
673 uint32_t value = dbus_read(target, address);
674 return value;
675 }
676
677 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
678 bool set_interrupt)
679 {
680 uint64_t dbus_value = DMCONTROL_HALTNOT | value;
681 if (set_interrupt)
682 dbus_value |= DMCONTROL_INTERRUPT;
683 dbus_write(target, dram_address(index), dbus_value);
684 }
685
686 /** Read the haltnot and interrupt bits. */
687 static bits_t read_bits(struct target *target)
688 {
689 uint64_t value;
690 dbus_status_t status;
691 uint16_t address_in;
692 riscv011_info_t *info = get_info(target);
693
694 bits_t err_result = {
695 .haltnot = 0,
696 .interrupt = 0
697 };
698
699 do {
700 unsigned i = 0;
701 do {
702 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
703 if (status == DBUS_STATUS_BUSY) {
704 if (address_in == (1<<info->addrbits) - 1 &&
705 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
706 LOG_ERROR("TDO seems to be stuck high.");
707 return err_result;
708 }
709 increase_dbus_busy_delay(target);
710 } else if (status == DBUS_STATUS_FAILED) {
711 /* TODO: return an actual error */
712 return err_result;
713 }
714 } while (status == DBUS_STATUS_BUSY && i++ < 256);
715
716 if (i >= 256) {
717 LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
718 return err_result;
719 }
720 } while (address_in > 0x10 && address_in != DMCONTROL);
721
722 bits_t result = {
723 .haltnot = get_field(value, DMCONTROL_HALTNOT),
724 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
725 };
726 return result;
727 }
728
729 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
730 {
731 time_t start = time(NULL);
732 if (ignore_first) {
733 /* Throw away the results of the first read, since they'll contain the
734 * result of the read that happened just before debugint was set.
735 * (Assuming the last scan before calling this function was one that
736 * sets debugint.) */
737 read_bits(target);
738 }
739 while (1) {
740 bits_t bits = read_bits(target);
741 if (!bits.interrupt)
742 return ERROR_OK;
743 if (time(NULL) - start > riscv_command_timeout_sec) {
744 LOG_ERROR("Timed out waiting for debug int to clear."
745 "Increase timeout with riscv set_command_timeout_sec.");
746 return ERROR_FAIL;
747 }
748 }
749 }
750
751 static int dram_check32(struct target *target, unsigned int index,
752 uint32_t expected)
753 {
754 uint16_t address = dram_address(index);
755 uint32_t actual = dbus_read(target, address);
756 if (expected != actual) {
757 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
758 expected, index, actual);
759 return ERROR_FAIL;
760 }
761 return ERROR_OK;
762 }
763
764 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
765 {
766 riscv011_info_t *info = get_info(target);
767 if (info->dram_cache[index].valid &&
768 info->dram_cache[index].data == data) {
769 /* This is already preset on the target. */
770 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
771 return;
772 }
773 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
774 info->dram_cache[index].data = data;
775 info->dram_cache[index].valid = true;
776 info->dram_cache[index].dirty = true;
777 }
778
779 static void cache_set(struct target *target, slot_t slot, uint64_t data)
780 {
781 unsigned int offset = slot_offset(target, slot);
782 cache_set32(target, offset, data);
783 if (riscv_xlen(target) > 32)
784 cache_set32(target, offset + 1, data >> 32);
785 }
786
787 static void cache_set_jump(struct target *target, unsigned int index)
788 {
789 cache_set32(target, index,
790 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
791 }
792
793 static void cache_set_load(struct target *target, unsigned int index,
794 unsigned int reg, slot_t slot)
795 {
796 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
797 cache_set32(target, index, load(target, reg, ZERO, offset));
798 }
799
800 static void cache_set_store(struct target *target, unsigned int index,
801 unsigned int reg, slot_t slot)
802 {
803 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
804 cache_set32(target, index, store(target, reg, ZERO, offset));
805 }
806
807 static void dump_debug_ram(struct target *target)
808 {
809 for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
810 uint32_t value = dram_read32(target, i);
811 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
812 }
813 }
814
815 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
816 static void cache_invalidate(struct target *target)
817 {
818 riscv011_info_t *info = get_info(target);
819 for (unsigned int i = 0; i < info->dramsize; i++) {
820 info->dram_cache[i].valid = false;
821 info->dram_cache[i].dirty = false;
822 }
823 }
824
825 /* Called by cache_write() after the program has run. Also call this if you're
826 * running programs without calling cache_write(). */
827 static void cache_clean(struct target *target)
828 {
829 riscv011_info_t *info = get_info(target);
830 for (unsigned int i = 0; i < info->dramsize; i++) {
831 if (i >= 4)
832 info->dram_cache[i].valid = false;
833 info->dram_cache[i].dirty = false;
834 }
835 }
836
837 static int cache_check(struct target *target)
838 {
839 riscv011_info_t *info = get_info(target);
840 int error = 0;
841
842 for (unsigned int i = 0; i < info->dramsize; i++) {
843 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
844 if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
845 error++;
846 }
847 }
848
849 if (error) {
850 dump_debug_ram(target);
851 return ERROR_FAIL;
852 }
853
854 return ERROR_OK;
855 }
856
857 /** Write cache to the target, and optionally run the program.
858 * Then read the value at address into the cache, assuming address < 128. */
859 #define CACHE_NO_READ 128
860 static int cache_write(struct target *target, unsigned int address, bool run)
861 {
862 LOG_DEBUG("enter");
863 riscv011_info_t *info = get_info(target);
864 scans_t *scans = scans_new(target, info->dramsize + 2);
865 if (!scans)
866 return ERROR_FAIL;
867
868 unsigned int last = info->dramsize;
869 for (unsigned int i = 0; i < info->dramsize; i++) {
870 if (info->dram_cache[i].dirty)
871 last = i;
872 }
873
874 if (last == info->dramsize) {
875 /* Nothing needs to be written to RAM. */
876 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
877
878 } else {
879 for (unsigned int i = 0; i < info->dramsize; i++) {
880 if (info->dram_cache[i].dirty) {
881 bool set_interrupt = (i == last && run);
882 scans_add_write32(scans, i, info->dram_cache[i].data,
883 set_interrupt);
884 }
885 }
886 }
887
888 if (run || address < CACHE_NO_READ) {
889 /* Throw away the results of the first read, since it'll contain the
890 * result of the read that happened just before debugint was set. */
891 scans_add_read32(scans, address, false);
892
893 /* This scan contains the results of the read the caller requested, as
894 * well as an interrupt bit worth looking at. */
895 scans_add_read32(scans, address, false);
896 }
897
898 int retval = scans_execute(scans);
899 if (retval != ERROR_OK) {
900 scans_delete(scans);
901 LOG_ERROR("JTAG execute failed.");
902 return retval;
903 }
904
905 int errors = 0;
906 for (unsigned int i = 0; i < scans->next_scan; i++) {
907 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
908 DBUS_OP_SIZE);
909 switch (status) {
910 case DBUS_STATUS_SUCCESS:
911 break;
912 case DBUS_STATUS_FAILED:
913 LOG_ERROR("Debug RAM write failed. Hardware error?");
914 scans_delete(scans);
915 return ERROR_FAIL;
916 case DBUS_STATUS_BUSY:
917 errors++;
918 break;
919 default:
920 LOG_ERROR("Got invalid bus access status: %d", status);
921 scans_delete(scans);
922 return ERROR_FAIL;
923 }
924 }
925
926 if (errors) {
927 increase_dbus_busy_delay(target);
928
929 /* Try again, using the slow careful code.
930 * Write all RAM, just to be extra cautious. */
931 for (unsigned int i = 0; i < info->dramsize; i++) {
932 if (i == last && run)
933 dram_write32(target, last, info->dram_cache[last].data, true);
934 else
935 dram_write32(target, i, info->dram_cache[i].data, false);
936 info->dram_cache[i].dirty = false;
937 }
938 if (run)
939 cache_clean(target);
940
941 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
942 LOG_ERROR("Debug interrupt didn't clear.");
943 dump_debug_ram(target);
944 scans_delete(scans);
945 return ERROR_FAIL;
946 }
947
948 } else {
949 if (run) {
950 cache_clean(target);
951 } else {
952 for (unsigned int i = 0; i < info->dramsize; i++)
953 info->dram_cache[i].dirty = false;
954 }
955
956 if (run || address < CACHE_NO_READ) {
957 int interrupt = scans_get_u32(scans, scans->next_scan-1,
958 DBUS_DATA_START + 33, 1);
959 if (interrupt) {
960 increase_interrupt_high_delay(target);
961 /* Slow path wait for it to clear. */
962 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
963 LOG_ERROR("Debug interrupt didn't clear.");
964 dump_debug_ram(target);
965 scans_delete(scans);
966 return ERROR_FAIL;
967 }
968 } else {
969 /* We read a useful value in that last scan. */
970 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
971 DBUS_ADDRESS_START, info->addrbits);
972 if (read_addr != address) {
973 LOG_INFO("Got data from 0x%x but expected it from 0x%x",
974 read_addr, address);
975 }
976 info->dram_cache[read_addr].data =
977 scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
978 info->dram_cache[read_addr].valid = true;
979 }
980 }
981 }
982
983 scans_delete(scans);
984 LOG_DEBUG("exit");
985
986 return ERROR_OK;
987 }
988
989 static uint32_t cache_get32(struct target *target, unsigned int address)
990 {
991 riscv011_info_t *info = get_info(target);
992 if (!info->dram_cache[address].valid) {
993 info->dram_cache[address].data = dram_read32(target, address);
994 info->dram_cache[address].valid = true;
995 }
996 return info->dram_cache[address].data;
997 }
998
999 static uint64_t cache_get(struct target *target, slot_t slot)
1000 {
1001 unsigned int offset = slot_offset(target, slot);
1002 uint64_t value = cache_get32(target, offset);
1003 if (riscv_xlen(target) > 32)
1004 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
1005 return value;
1006 }
1007
1008 /* Write instruction that jumps from the specified word in Debug RAM to resume
1009 * in Debug ROM. */
1010 static void dram_write_jump(struct target *target, unsigned int index,
1011 bool set_interrupt)
1012 {
1013 dram_write32(target, index,
1014 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
1015 set_interrupt);
1016 }
1017
1018 static int wait_for_state(struct target *target, enum target_state state)
1019 {
1020 time_t start = time(NULL);
1021 while (1) {
1022 int result = riscv011_poll(target);
1023 if (result != ERROR_OK)
1024 return result;
1025 if (target->state == state)
1026 return ERROR_OK;
1027 if (time(NULL) - start > riscv_command_timeout_sec) {
1028 LOG_ERROR("Timed out waiting for state %d. "
1029 "Increase timeout with riscv set_command_timeout_sec.", state);
1030 return ERROR_FAIL;
1031 }
1032 }
1033 }
1034
1035 static int read_remote_csr(struct target *target, uint64_t *value, uint32_t csr)
1036 {
1037 riscv011_info_t *info = get_info(target);
1038 cache_set32(target, 0, csrr(S0, csr));
1039 cache_set_store(target, 1, S0, SLOT0);
1040 cache_set_jump(target, 2);
1041 if (cache_write(target, 4, true) != ERROR_OK)
1042 return ERROR_FAIL;
1043 *value = cache_get(target, SLOT0);
1044 LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1045
1046 uint32_t exception = cache_get32(target, info->dramsize-1);
1047 if (exception) {
1048 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1049 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1050 *value = ~0;
1051 return ERROR_FAIL;
1052 }
1053
1054 return ERROR_OK;
1055 }
1056
1057 static int write_remote_csr(struct target *target, uint32_t csr, uint64_t value)
1058 {
1059 LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1060 cache_set_load(target, 0, S0, SLOT0);
1061 cache_set32(target, 1, csrw(S0, csr));
1062 cache_set_jump(target, 2);
1063 cache_set(target, SLOT0, value);
1064 if (cache_write(target, 4, true) != ERROR_OK)
1065 return ERROR_FAIL;
1066
1067 return ERROR_OK;
1068 }
1069
1070 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1071 {
1072 cache_set_load(target, 0, gpr, SLOT0);
1073 cache_set_jump(target, 1);
1074 cache_set(target, SLOT0, value);
1075 if (cache_write(target, 4, true) != ERROR_OK)
1076 return ERROR_FAIL;
1077 return ERROR_OK;
1078 }
1079
1080 static int maybe_read_tselect(struct target *target)
1081 {
1082 riscv011_info_t *info = get_info(target);
1083
1084 if (info->tselect_dirty) {
1085 int result = read_remote_csr(target, &info->tselect, CSR_TSELECT);
1086 if (result != ERROR_OK)
1087 return result;
1088 info->tselect_dirty = false;
1089 }
1090
1091 return ERROR_OK;
1092 }
1093
1094 static int maybe_write_tselect(struct target *target)
1095 {
1096 riscv011_info_t *info = get_info(target);
1097
1098 if (!info->tselect_dirty) {
1099 int result = write_remote_csr(target, CSR_TSELECT, info->tselect);
1100 if (result != ERROR_OK)
1101 return result;
1102 info->tselect_dirty = true;
1103 }
1104
1105 return ERROR_OK;
1106 }
1107
1108 static int execute_resume(struct target *target, bool step)
1109 {
1110 riscv011_info_t *info = get_info(target);
1111
1112 LOG_DEBUG("step=%d", step);
1113
1114 maybe_write_tselect(target);
1115
1116 /* TODO: check if dpc is dirty (which also is true if an exception was hit
1117 * at any time) */
1118 cache_set_load(target, 0, S0, SLOT0);
1119 cache_set32(target, 1, csrw(S0, CSR_DPC));
1120 cache_set_jump(target, 2);
1121 cache_set(target, SLOT0, info->dpc);
1122 if (cache_write(target, 4, true) != ERROR_OK)
1123 return ERROR_FAIL;
1124
1125 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1126 if (mstatus_reg->valid) {
1127 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1128 if (mstatus_user != info->mstatus_actual) {
1129 cache_set_load(target, 0, S0, SLOT0);
1130 cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1131 cache_set_jump(target, 2);
1132 cache_set(target, SLOT0, mstatus_user);
1133 if (cache_write(target, 4, true) != ERROR_OK)
1134 return ERROR_FAIL;
1135 }
1136 }
1137
1138 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1139 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1140 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1141 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1142 info->dcsr &= ~DCSR_HALT;
1143
1144 if (step)
1145 info->dcsr |= DCSR_STEP;
1146 else
1147 info->dcsr &= ~DCSR_STEP;
1148
1149 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1150 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1151 dram_write32(target, 2, fence_i(), false);
1152 dram_write_jump(target, 3, false);
1153
1154 /* Write DCSR value, set interrupt and clear haltnot. */
1155 uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1156 dbus_write(target, dram_address(4), dbus_value);
1157
1158 cache_invalidate(target);
1159
1160 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1161 LOG_ERROR("Debug interrupt didn't clear.");
1162 return ERROR_FAIL;
1163 }
1164
1165 target->state = TARGET_RUNNING;
1166 register_cache_invalidate(target->reg_cache);
1167
1168 return ERROR_OK;
1169 }
1170
1171 /* Execute a step, and wait for reentry into Debug Mode. */
1172 static int full_step(struct target *target, bool announce)
1173 {
1174 int result = execute_resume(target, true);
1175 if (result != ERROR_OK)
1176 return result;
1177 time_t start = time(NULL);
1178 while (1) {
1179 result = poll_target(target, announce);
1180 if (result != ERROR_OK)
1181 return result;
1182 if (target->state != TARGET_DEBUG_RUNNING)
1183 break;
1184 if (time(NULL) - start > riscv_command_timeout_sec) {
1185 LOG_ERROR("Timed out waiting for step to complete."
1186 "Increase timeout with riscv set_command_timeout_sec");
1187 return ERROR_FAIL;
1188 }
1189 }
1190 return ERROR_OK;
1191 }
1192
1193 static int resume(struct target *target, int debug_execution, bool step)
1194 {
1195 if (debug_execution) {
1196 LOG_ERROR("TODO: debug_execution is true");
1197 return ERROR_FAIL;
1198 }
1199
1200 return execute_resume(target, step);
1201 }
1202
1203 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1204 {
1205 struct reg *r = &target->reg_cache->reg_list[number];
1206 if (!r->valid) {
1207 LOG_ERROR("Register cache entry for %d is invalid!", number);
1208 assert(r->valid);
1209 }
1210 uint64_t value = buf_get_u64(r->value, 0, r->size);
1211 LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1212 return value;
1213 }
1214
1215 static void reg_cache_set(struct target *target, unsigned int number,
1216 uint64_t value)
1217 {
1218 struct reg *r = &target->reg_cache->reg_list[number];
1219 LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1220 r->valid = true;
1221 buf_set_u64(r->value, 0, r->size, value);
1222 }
1223
1224 static int update_mstatus_actual(struct target *target)
1225 {
1226 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1227 if (mstatus_reg->valid) {
1228 /* We previously made it valid. */
1229 return ERROR_OK;
1230 }
1231
1232 /* Force reading the register. In that process mstatus_actual will be
1233 * updated. */
1234 riscv_reg_t mstatus;
1235 return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
1236 }
1237
1238 /*** OpenOCD target functions. ***/
1239
1240 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1241 {
1242 riscv011_info_t *info = get_info(target);
1243 if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1244 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1245 cache_set_store(target, 1, S0, SLOT0);
1246 cache_set_jump(target, 2);
1247 } else {
1248 LOG_ERROR("Don't know how to read register %d", regnum);
1249 return ERROR_FAIL;
1250 }
1251
1252 if (cache_write(target, 4, true) != ERROR_OK)
1253 return ERROR_FAIL;
1254
1255 uint32_t exception = cache_get32(target, info->dramsize-1);
1256 if (exception) {
1257 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1258 *value = ~0;
1259 return ERROR_FAIL;
1260 }
1261
1262 *value = cache_get(target, SLOT0);
1263 LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1264
1265 if (regnum == GDB_REGNO_MSTATUS)
1266 info->mstatus_actual = *value;
1267
1268 return ERROR_OK;
1269 }
1270
1271 /* Write the register. No caching or games. */
1272 static int register_write(struct target *target, unsigned int number,
1273 uint64_t value)
1274 {
1275 riscv011_info_t *info = get_info(target);
1276
1277 maybe_write_tselect(target);
1278
1279 if (number == S0) {
1280 cache_set_load(target, 0, S0, SLOT0);
1281 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH0));
1282 cache_set_jump(target, 2);
1283 } else if (number == S1) {
1284 cache_set_load(target, 0, S0, SLOT0);
1285 cache_set_store(target, 1, S0, SLOT_LAST);
1286 cache_set_jump(target, 2);
1287 } else if (number <= GDB_REGNO_XPR31) {
1288 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1289 cache_set_jump(target, 1);
1290 } else if (number == GDB_REGNO_PC) {
1291 info->dpc = value;
1292 return ERROR_OK;
1293 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1294 int result = update_mstatus_actual(target);
1295 if (result != ERROR_OK)
1296 return result;
1297 unsigned i = 0;
1298 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1299 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1300 cache_set_load(target, i++, S0, SLOT1);
1301 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1302 cache_set(target, SLOT1, info->mstatus_actual);
1303 }
1304
1305 if (riscv_xlen(target) == 32)
1306 cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1307 else
1308 cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1309 cache_set_jump(target, i++);
1310 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1311 cache_set_load(target, 0, S0, SLOT0);
1312 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1313 cache_set_jump(target, 2);
1314
1315 if (number == GDB_REGNO_MSTATUS)
1316 info->mstatus_actual = value;
1317 } else if (number == GDB_REGNO_PRIV) {
1318 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1319 return ERROR_OK;
1320 } else {
1321 LOG_ERROR("Don't know how to write register %d", number);
1322 return ERROR_FAIL;
1323 }
1324
1325 cache_set(target, SLOT0, value);
1326 if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1327 return ERROR_FAIL;
1328
1329 uint32_t exception = cache_get32(target, info->dramsize-1);
1330 if (exception) {
1331 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1332 gdb_regno_name(number));
1333 return ERROR_FAIL;
1334 }
1335
1336 return ERROR_OK;
1337 }
1338
1339 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
1340 int regid)
1341 {
1342 assert(hartid == 0);
1343 riscv011_info_t *info = get_info(target);
1344
1345 maybe_write_tselect(target);
1346
1347 if (regid <= GDB_REGNO_XPR31) {
1348 *value = reg_cache_get(target, regid);
1349 } else if (regid == GDB_REGNO_PC) {
1350 *value = info->dpc;
1351 } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1352 int result = update_mstatus_actual(target);
1353 if (result != ERROR_OK)
1354 return result;
1355 unsigned i = 0;
1356 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1357 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1358 cache_set_load(target, i++, S0, SLOT1);
1359 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1360 cache_set(target, SLOT1, info->mstatus_actual);
1361 }
1362
1363 if (riscv_xlen(target) == 32)
1364 cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1365 else
1366 cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1367 cache_set_jump(target, i++);
1368
1369 if (cache_write(target, 4, true) != ERROR_OK)
1370 return ERROR_FAIL;
1371 } else if (regid == GDB_REGNO_PRIV) {
1372 *value = get_field(info->dcsr, DCSR_PRV);
1373 } else {
1374 int result = register_read(target, value, regid);
1375 if (result != ERROR_OK)
1376 return result;
1377 }
1378
1379 if (regid == GDB_REGNO_MSTATUS)
1380 target->reg_cache->reg_list[regid].valid = true;
1381
1382 return ERROR_OK;
1383 }
1384
1385 static int set_register(struct target *target, int hartid, int regid,
1386 uint64_t value)
1387 {
1388 assert(hartid == 0);
1389 return register_write(target, regid, value);
1390 }
1391
1392 static int halt(struct target *target)
1393 {
1394 LOG_DEBUG("riscv_halt()");
1395 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1396
1397 cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1398 cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1399 cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1400 cache_set_jump(target, 3);
1401
1402 if (cache_write(target, 4, true) != ERROR_OK) {
1403 LOG_ERROR("cache_write() failed.");
1404 return ERROR_FAIL;
1405 }
1406
1407 return ERROR_OK;
1408 }
1409
1410 static void deinit_target(struct target *target)
1411 {
1412 LOG_DEBUG("riscv_deinit_target()");
1413 riscv_info_t *info = (riscv_info_t *) target->arch_info;
1414 free(info->version_specific);
1415 info->version_specific = NULL;
1416 }
1417
1418 static int strict_step(struct target *target, bool announce)
1419 {
1420 LOG_DEBUG("enter");
1421
1422 struct watchpoint *watchpoint = target->watchpoints;
1423 while (watchpoint) {
1424 riscv_remove_watchpoint(target, watchpoint);
1425 watchpoint = watchpoint->next;
1426 }
1427
1428 int result = full_step(target, announce);
1429 if (result != ERROR_OK)
1430 return result;
1431
1432 watchpoint = target->watchpoints;
1433 while (watchpoint) {
1434 riscv_add_watchpoint(target, watchpoint);
1435 watchpoint = watchpoint->next;
1436 }
1437
1438 return ERROR_OK;
1439 }
1440
1441 static int step(struct target *target, int current, target_addr_t address,
1442 int handle_breakpoints)
1443 {
1444 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1445
1446 if (!current) {
1447 if (riscv_xlen(target) > 32) {
1448 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1449 riscv_xlen(target));
1450 }
1451 int result = register_write(target, GDB_REGNO_PC, address);
1452 if (result != ERROR_OK)
1453 return result;
1454 }
1455
1456 if (handle_breakpoints) {
1457 int result = strict_step(target, true);
1458 if (result != ERROR_OK)
1459 return result;
1460 } else {
1461 return full_step(target, false);
1462 }
1463
1464 return ERROR_OK;
1465 }
1466
1467 static int examine(struct target *target)
1468 {
1469 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1470
1471 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1472 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1473 LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1474 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1475 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1476 if (dtmcontrol == 0) {
1477 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1478 return ERROR_FAIL;
1479 }
1480 if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1481 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1482 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1483 return ERROR_FAIL;
1484 }
1485
1486 RISCV_INFO(r);
1487
1488 riscv011_info_t *info = get_info(target);
1489 info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1490 info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1491 if (info->dtmcontrol_idle == 0) {
1492 /* Some old SiFive cores don't set idle but need it to be 1. */
1493 uint32_t idcode = idcode_scan(target);
1494 if (idcode == 0x10e31913)
1495 info->dtmcontrol_idle = 1;
1496 }
1497
1498 uint32_t dminfo = dbus_read(target, DMINFO);
1499 LOG_DEBUG("dminfo: 0x%08x", dminfo);
1500 LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1501 LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1502 LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1503 LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1504 LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1505 LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1506 LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1507 LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1508 LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1509 LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1510 LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1511 LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
1512
1513 if (get_field(dminfo, DMINFO_VERSION) != 1) {
1514 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1515 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1516 return ERROR_FAIL;
1517 }
1518
1519 info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1520
1521 if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1522 LOG_ERROR("Authentication required by RISC-V core but not "
1523 "supported by OpenOCD. dminfo=0x%x", dminfo);
1524 return ERROR_FAIL;
1525 }
1526
1527 /* Pretend this is a 32-bit system until we have found out the true value. */
1528 r->xlen[0] = 32;
1529
1530 /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1531 cache_set32(target, 0, xori(S1, ZERO, -1));
1532 /* 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff */
1533 cache_set32(target, 1, srli(S1, S1, 31));
1534 /* 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff */
1535 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1536 cache_set32(target, 3, srli(S1, S1, 31));
1537 /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
1538 cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1539 cache_set_jump(target, 5);
1540 for (unsigned i = 6; i < info->dramsize; i++)
1541 cache_set32(target, i, i * 0x01020304);
1542
1543 cache_write(target, 0, false);
1544
1545 /* Check that we can actually read/write dram. */
1546 if (cache_check(target) != ERROR_OK)
1547 return ERROR_FAIL;
1548
1549 cache_write(target, 0, true);
1550 cache_invalidate(target);
1551
1552 uint32_t word0 = cache_get32(target, 0);
1553 uint32_t word1 = cache_get32(target, 1);
1554 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1555 if (word0 == 1 && word1 == 0) {
1556 generic_info->xlen[0] = 32;
1557 } else if (word0 == 0xffffffff && word1 == 3) {
1558 generic_info->xlen[0] = 64;
1559 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1560 generic_info->xlen[0] = 128;
1561 } else {
1562 uint32_t exception = cache_get32(target, info->dramsize-1);
1563 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1564 word0, word1, exception);
1565 dump_debug_ram(target);
1566 return ERROR_FAIL;
1567 }
1568 LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1569
1570 if (read_remote_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) {
1571 const unsigned old_csr_misa = 0xf10;
1572 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1573 old_csr_misa);
1574 if (read_remote_csr(target, &r->misa[0], old_csr_misa) != ERROR_OK) {
1575 /* Maybe this is an old core that still has $misa at the old
1576 * address. */
1577 LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1578 return ERROR_FAIL;
1579 }
1580 }
1581
1582 /* Update register list to match discovered XLEN/supported extensions. */
1583 riscv_init_registers(target);
1584
1585 info->never_halted = true;
1586
1587 int result = riscv011_poll(target);
1588 if (result != ERROR_OK)
1589 return result;
1590
1591 target_set_examined(target);
1592 riscv_set_current_hartid(target, 0);
1593 for (size_t i = 0; i < 32; ++i)
1594 reg_cache_set(target, i, -1);
1595 LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1596 riscv_xlen(target), r->misa[0]);
1597
1598 return ERROR_OK;
1599 }
1600
1601 static riscv_error_t handle_halt_routine(struct target *target)
1602 {
1603 riscv011_info_t *info = get_info(target);
1604
1605 scans_t *scans = scans_new(target, 256);
1606 if (!scans)
1607 return RE_FAIL;
1608
1609 /* Read all GPRs as fast as we can, because gdb is going to ask for them
1610 * anyway. Reading them one at a time is much slower. */
1611
1612 /* Write the jump back to address 1. */
1613 scans_add_write_jump(scans, 1, false);
1614 for (int reg = 1; reg < 32; reg++) {
1615 if (reg == S0 || reg == S1)
1616 continue;
1617
1618 /* Write store instruction. */
1619 scans_add_write_store(scans, 0, reg, SLOT0, true);
1620
1621 /* Read value. */
1622 scans_add_read(scans, SLOT0, false);
1623 }
1624
1625 /* Write store of s0 at index 1. */
1626 scans_add_write_store(scans, 1, S0, SLOT0, false);
1627 /* Write jump at index 2. */
1628 scans_add_write_jump(scans, 2, false);
1629
1630 /* Read S1 from debug RAM */
1631 scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1632 /* Read value. */
1633 scans_add_read(scans, SLOT0, false);
1634
1635 /* Read S0 from dscratch */
1636 unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR};
1637 for (unsigned int i = 0; i < DIM(csr); i++) {
1638 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1639 scans_add_read(scans, SLOT0, false);
1640 }
1641
1642 /* Final read to get the last value out. */
1643 scans_add_read32(scans, 4, false);
1644
1645 int retval = scans_execute(scans);
1646 if (retval != ERROR_OK) {
1647 LOG_ERROR("JTAG execute failed: %d", retval);
1648 goto error;
1649 }
1650
1651 unsigned int dbus_busy = 0;
1652 unsigned int interrupt_set = 0;
1653 unsigned result = 0;
1654 uint64_t value = 0;
1655 reg_cache_set(target, 0, 0);
1656 /* The first scan result is the result from something old we don't care
1657 * about. */
1658 for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1659 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1660 DBUS_OP_SIZE);
1661 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1662 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1663 info->addrbits);
1664 switch (status) {
1665 case DBUS_STATUS_SUCCESS:
1666 break;
1667 case DBUS_STATUS_FAILED:
1668 LOG_ERROR("Debug access failed. Hardware error?");
1669 goto error;
1670 case DBUS_STATUS_BUSY:
1671 dbus_busy++;
1672 break;
1673 default:
1674 LOG_ERROR("Got invalid bus access status: %d", status);
1675 goto error;
1676 }
1677 if (data & DMCONTROL_INTERRUPT) {
1678 interrupt_set++;
1679 break;
1680 }
1681 if (address == 4 || address == 5) {
1682 unsigned int reg;
1683 switch (result) {
1684 case 0:
1685 reg = 1;
1686 break;
1687 case 1:
1688 reg = 2;
1689 break;
1690 case 2:
1691 reg = 3;
1692 break;
1693 case 3:
1694 reg = 4;
1695 break;
1696 case 4:
1697 reg = 5;
1698 break;
1699 case 5:
1700 reg = 6;
1701 break;
1702 case 6:
1703 reg = 7;
1704 break;
1705 /* S0 */
1706 /* S1 */
1707 case 7:
1708 reg = 10;
1709 break;
1710 case 8:
1711 reg = 11;
1712 break;
1713 case 9:
1714 reg = 12;
1715 break;
1716 case 10:
1717 reg = 13;
1718 break;
1719 case 11:
1720 reg = 14;
1721 break;
1722 case 12:
1723 reg = 15;
1724 break;
1725 case 13:
1726 reg = 16;
1727 break;
1728 case 14:
1729 reg = 17;
1730 break;
1731 case 15:
1732 reg = 18;
1733 break;
1734 case 16:
1735 reg = 19;
1736 break;
1737 case 17:
1738 reg = 20;
1739 break;
1740 case 18:
1741 reg = 21;
1742 break;
1743 case 19:
1744 reg = 22;
1745 break;
1746 case 20:
1747 reg = 23;
1748 break;
1749 case 21:
1750 reg = 24;
1751 break;
1752 case 22:
1753 reg = 25;
1754 break;
1755 case 23:
1756 reg = 26;
1757 break;
1758 case 24:
1759 reg = 27;
1760 break;
1761 case 25:
1762 reg = 28;
1763 break;
1764 case 26:
1765 reg = 29;
1766 break;
1767 case 27:
1768 reg = 30;
1769 break;
1770 case 28:
1771 reg = 31;
1772 break;
1773 case 29:
1774 reg = S1;
1775 break;
1776 case 30:
1777 reg = S0;
1778 break;
1779 case 31:
1780 reg = CSR_DPC;
1781 break;
1782 case 32:
1783 reg = CSR_DCSR;
1784 break;
1785 default:
1786 assert(0);
1787 LOG_ERROR("Got invalid register result %d", result);
1788 goto error;
1789 }
1790 if (riscv_xlen(target) == 32) {
1791 reg_cache_set(target, reg, data & 0xffffffff);
1792 result++;
1793 } else if (riscv_xlen(target) == 64) {
1794 if (address == 4) {
1795 value = data & 0xffffffff;
1796 } else if (address == 5) {
1797 reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1798 value = 0;
1799 result++;
1800 }
1801 }
1802 }
1803 }
1804
1805 scans_delete(scans);
1806
1807 if (dbus_busy) {
1808 increase_dbus_busy_delay(target);
1809 return RE_AGAIN;
1810 }
1811 if (interrupt_set) {
1812 increase_interrupt_high_delay(target);
1813 return RE_AGAIN;
1814 }
1815
1816 /* TODO: get rid of those 2 variables and talk to the cache directly. */
1817 info->dpc = reg_cache_get(target, CSR_DPC);
1818 info->dcsr = reg_cache_get(target, CSR_DCSR);
1819
1820 cache_invalidate(target);
1821
1822 return RE_OK;
1823
1824 error:
1825 scans_delete(scans);
1826 return RE_FAIL;
1827 }
1828
1829 static int handle_halt(struct target *target, bool announce)
1830 {
1831 riscv011_info_t *info = get_info(target);
1832 target->state = TARGET_HALTED;
1833
1834 riscv_error_t re;
1835 do {
1836 re = handle_halt_routine(target);
1837 } while (re == RE_AGAIN);
1838 if (re != RE_OK) {
1839 LOG_ERROR("handle_halt_routine failed");
1840 return ERROR_FAIL;
1841 }
1842
1843 int cause = get_field(info->dcsr, DCSR_CAUSE);
1844 switch (cause) {
1845 case DCSR_CAUSE_SWBP:
1846 target->debug_reason = DBG_REASON_BREAKPOINT;
1847 break;
1848 case DCSR_CAUSE_HWBP:
1849 target->debug_reason = DBG_REASON_WATCHPOINT;
1850 break;
1851 case DCSR_CAUSE_DEBUGINT:
1852 target->debug_reason = DBG_REASON_DBGRQ;
1853 break;
1854 case DCSR_CAUSE_STEP:
1855 target->debug_reason = DBG_REASON_SINGLESTEP;
1856 break;
1857 case DCSR_CAUSE_HALT:
1858 default:
1859 LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1860 cause, info->dcsr);
1861 }
1862
1863 if (info->never_halted) {
1864 info->never_halted = false;
1865
1866 int result = maybe_read_tselect(target);
1867 if (result != ERROR_OK)
1868 return result;
1869 riscv_enumerate_triggers(target);
1870 }
1871
1872 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1873 int retval;
1874 if (riscv_semihosting(target, &retval) != 0)
1875 return retval;
1876 }
1877
1878 if (announce)
1879 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1880
1881 const char *cause_string[] = {
1882 "none",
1883 "software breakpoint",
1884 "hardware trigger",
1885 "debug interrupt",
1886 "step",
1887 "halt"
1888 };
1889 /* This is logged to the user so that gdb will show it when a user types
1890 * 'monitor reset init'. At that time gdb appears to have the pc cached
1891 * still so if a user manually inspects the pc it will still have the old
1892 * value. */
1893 LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1894
1895 return ERROR_OK;
1896 }
1897
1898 static int poll_target(struct target *target, bool announce)
1899 {
1900 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1901
1902 /* Inhibit debug logging during poll(), which isn't usually interesting and
1903 * just fills up the screen/logs with clutter. */
1904 int old_debug_level = debug_level;
1905 if (debug_level >= LOG_LVL_DEBUG)
1906 debug_level = LOG_LVL_INFO;
1907 bits_t bits = read_bits(target);
1908 debug_level = old_debug_level;
1909
1910 if (bits.haltnot && bits.interrupt) {
1911 target->state = TARGET_DEBUG_RUNNING;
1912 LOG_DEBUG("debug running");
1913 } else if (bits.haltnot && !bits.interrupt) {
1914 if (target->state != TARGET_HALTED)
1915 return handle_halt(target, announce);
1916 } else if (!bits.haltnot && bits.interrupt) {
1917 /* Target is halting. There is no state for that, so don't change anything. */
1918 LOG_DEBUG("halting");
1919 } else if (!bits.haltnot && !bits.interrupt) {
1920 target->state = TARGET_RUNNING;
1921 }
1922
1923 return ERROR_OK;
1924 }
1925
1926 static int riscv011_poll(struct target *target)
1927 {
1928 return poll_target(target, true);
1929 }
1930
1931 static int riscv011_resume(struct target *target, int current,
1932 target_addr_t address, int handle_breakpoints, int debug_execution)
1933 {
1934 RISCV_INFO(r);
1935 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1936
1937 r->prepped = false;
1938 return resume(target, debug_execution, false);
1939 }
1940
1941 static int assert_reset(struct target *target)
1942 {
1943 riscv011_info_t *info = get_info(target);
1944 /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1945
1946 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1947
1948 /* The only assumption we can make is that the TAP was reset. */
1949 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1950 LOG_ERROR("Debug interrupt didn't clear.");
1951 return ERROR_FAIL;
1952 }
1953
1954 /* Not sure what we should do when there are multiple cores.
1955 * Here just reset the single hart we're talking to. */
1956 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1957 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1958 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1959 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1960 info->dcsr |= DCSR_HALT;
1961 if (target->reset_halt)
1962 info->dcsr |= DCSR_NDRESET;
1963 else
1964 info->dcsr |= DCSR_FULLRESET;
1965 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1966 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1967 /* We shouldn't actually need the jump because a reset should happen. */
1968 dram_write_jump(target, 2, false);
1969 dram_write32(target, 4, info->dcsr, true);
1970 cache_invalidate(target);
1971
1972 target->state = TARGET_RESET;
1973
1974 return ERROR_OK;
1975 }
1976
1977 static int deassert_reset(struct target *target)
1978 {
1979 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1980 if (target->reset_halt)
1981 return wait_for_state(target, TARGET_HALTED);
1982 else
1983 return wait_for_state(target, TARGET_RUNNING);
1984 }
1985
1986 static int read_memory(struct target *target, target_addr_t address,
1987 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
1988 {
1989 if (increment != size) {
1990 LOG_ERROR("read_memory with custom increment not implemented");
1991 return ERROR_NOT_IMPLEMENTED;
1992 }
1993
1994 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1995
1996 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
1997 switch (size) {
1998 case 1:
1999 cache_set32(target, 1, lb(S1, S0, 0));
2000 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2001 break;
2002 case 2:
2003 cache_set32(target, 1, lh(S1, S0, 0));
2004 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2005 break;
2006 case 4:
2007 cache_set32(target, 1, lw(S1, S0, 0));
2008 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2009 break;
2010 default:
2011 LOG_ERROR("Unsupported size: %d", size);
2012 return ERROR_FAIL;
2013 }
2014 cache_set_jump(target, 3);
2015 cache_write(target, CACHE_NO_READ, false);
2016
2017 riscv011_info_t *info = get_info(target);
2018 const unsigned max_batch_size = 256;
2019 scans_t *scans = scans_new(target, max_batch_size);
2020 if (!scans)
2021 return ERROR_FAIL;
2022
2023 uint32_t result_value = 0x777;
2024 uint32_t i = 0;
2025 while (i < count + 3) {
2026 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2027 scans_reset(scans);
2028
2029 for (unsigned int j = 0; j < batch_size; j++) {
2030 if (i + j == count) {
2031 /* Just insert a read so we can scan out the last value. */
2032 scans_add_read32(scans, 4, false);
2033 } else if (i + j >= count + 1) {
2034 /* And check for errors. */
2035 scans_add_read32(scans, info->dramsize-1, false);
2036 } else {
2037 /* Write the next address and set interrupt. */
2038 uint32_t offset = size * (i + j);
2039 scans_add_write32(scans, 4, address + offset, true);
2040 }
2041 }
2042
2043 int retval = scans_execute(scans);
2044 if (retval != ERROR_OK) {
2045 LOG_ERROR("JTAG execute failed: %d", retval);
2046 goto error;
2047 }
2048
2049 int dbus_busy = 0;
2050 int execute_busy = 0;
2051 for (unsigned int j = 0; j < batch_size; j++) {
2052 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2053 DBUS_OP_SIZE);
2054 switch (status) {
2055 case DBUS_STATUS_SUCCESS:
2056 break;
2057 case DBUS_STATUS_FAILED:
2058 LOG_ERROR("Debug RAM write failed. Hardware error?");
2059 goto error;
2060 case DBUS_STATUS_BUSY:
2061 dbus_busy++;
2062 break;
2063 default:
2064 LOG_ERROR("Got invalid bus access status: %d", status);
2065 return ERROR_FAIL;
2066 }
2067 uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2068 DBUS_DATA_SIZE);
2069 if (data & DMCONTROL_INTERRUPT)
2070 execute_busy++;
2071 if (i + j == count + 2) {
2072 result_value = data;
2073 } else if (i + j > 1) {
2074 uint32_t offset = size * (i + j - 2);
2075 switch (size) {
2076 case 1:
2077 buffer[offset] = data;
2078 break;
2079 case 2:
2080 buffer[offset] = data;
2081 buffer[offset+1] = data >> 8;
2082 break;
2083 case 4:
2084 buffer[offset] = data;
2085 buffer[offset+1] = data >> 8;
2086 buffer[offset+2] = data >> 16;
2087 buffer[offset+3] = data >> 24;
2088 break;
2089 }
2090 }
2091 LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2092 }
2093 if (dbus_busy)
2094 increase_dbus_busy_delay(target);
2095 if (execute_busy)
2096 increase_interrupt_high_delay(target);
2097 if (dbus_busy || execute_busy) {
2098 wait_for_debugint_clear(target, false);
2099
2100 /* Retry. */
2101 LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2102 " with more delays", address + size * i);
2103 } else {
2104 i += batch_size;
2105 }
2106 }
2107
2108 if (result_value != 0) {
2109 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2110 TARGET_PRIxADDR, result_value, address + size * (count-1));
2111 if (count > 1) {
2112 LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2113 " and 0x%" TARGET_PRIxADDR " as well, but we "
2114 "didn't check then.)",
2115 address, address + size * (count-2) + size - 1);
2116 }
2117 goto error;
2118 }
2119
2120 scans_delete(scans);
2121 cache_clean(target);
2122 return ERROR_OK;
2123
2124 error:
2125 scans_delete(scans);
2126 cache_clean(target);
2127 return ERROR_FAIL;
2128 }
2129
2130 static int setup_write_memory(struct target *target, uint32_t size)
2131 {
2132 switch (size) {
2133 case 1:
2134 cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2135 cache_set32(target, 1, sb(S0, T0, 0));
2136 break;
2137 case 2:
2138 cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2139 cache_set32(target, 1, sh(S0, T0, 0));
2140 break;
2141 case 4:
2142 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2143 cache_set32(target, 1, sw(S0, T0, 0));
2144 break;
2145 default:
2146 LOG_ERROR("Unsupported size: %d", size);
2147 return ERROR_FAIL;
2148 }
2149 cache_set32(target, 2, addi(T0, T0, size));
2150 cache_set_jump(target, 3);
2151 cache_write(target, 4, false);
2152
2153 return ERROR_OK;
2154 }
2155
2156 static int write_memory(struct target *target, target_addr_t address,
2157 uint32_t size, uint32_t count, const uint8_t *buffer)
2158 {
2159 riscv011_info_t *info = get_info(target);
2160 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2161
2162 /* Set up the address. */
2163 cache_set_store(target, 0, T0, SLOT1);
2164 cache_set_load(target, 1, T0, SLOT0);
2165 cache_set_jump(target, 2);
2166 cache_set(target, SLOT0, address);
2167 if (cache_write(target, 5, true) != ERROR_OK)
2168 return ERROR_FAIL;
2169
2170 uint64_t t0 = cache_get(target, SLOT1);
2171 LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2172
2173 if (setup_write_memory(target, size) != ERROR_OK)
2174 return ERROR_FAIL;
2175
2176 const unsigned max_batch_size = 256;
2177 scans_t *scans = scans_new(target, max_batch_size);
2178 if (!scans)
2179 return ERROR_FAIL;
2180
2181 uint32_t result_value = 0x777;
2182 uint32_t i = 0;
2183 while (i < count + 2) {
2184 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2185 scans_reset(scans);
2186
2187 for (unsigned int j = 0; j < batch_size; j++) {
2188 if (i + j >= count) {
2189 /* Check for an exception. */
2190 scans_add_read32(scans, info->dramsize-1, false);
2191 } else {
2192 /* Write the next value and set interrupt. */
2193 uint32_t value;
2194 uint32_t offset = size * (i + j);
2195 switch (size) {
2196 case 1:
2197 value = buffer[offset];
2198 break;
2199 case 2:
2200 value = buffer[offset] |
2201 (buffer[offset+1] << 8);
2202 break;
2203 case 4:
2204 value = buffer[offset] |
2205 ((uint32_t) buffer[offset+1] << 8) |
2206 ((uint32_t) buffer[offset+2] << 16) |
2207 ((uint32_t) buffer[offset+3] << 24);
2208 break;
2209 default:
2210 goto error;
2211 }
2212
2213 scans_add_write32(scans, 4, value, true);
2214 }
2215 }
2216
2217 int retval = scans_execute(scans);
2218 if (retval != ERROR_OK) {
2219 LOG_ERROR("JTAG execute failed: %d", retval);
2220 goto error;
2221 }
2222
2223 int dbus_busy = 0;
2224 int execute_busy = 0;
2225 for (unsigned int j = 0; j < batch_size; j++) {
2226 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2227 DBUS_OP_SIZE);
2228 switch (status) {
2229 case DBUS_STATUS_SUCCESS:
2230 break;
2231 case DBUS_STATUS_FAILED:
2232 LOG_ERROR("Debug RAM write failed. Hardware error?");
2233 goto error;
2234 case DBUS_STATUS_BUSY:
2235 dbus_busy++;
2236 break;
2237 default:
2238 LOG_ERROR("Got invalid bus access status: %d", status);
2239 return ERROR_FAIL;
2240 }
2241 int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2242 if (interrupt)
2243 execute_busy++;
2244 if (i + j == count + 1)
2245 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2246 }
2247 if (dbus_busy)
2248 increase_dbus_busy_delay(target);
2249 if (execute_busy)
2250 increase_interrupt_high_delay(target);
2251 if (dbus_busy || execute_busy) {
2252 wait_for_debugint_clear(target, false);
2253
2254 /* Retry.
2255 * Set t0 back to what it should have been at the beginning of this
2256 * batch. */
2257 LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2258 " with more delays", address + size * i);
2259
2260 cache_clean(target);
2261
2262 if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2263 goto error;
2264
2265 if (setup_write_memory(target, size) != ERROR_OK)
2266 goto error;
2267 } else {
2268 i += batch_size;
2269 }
2270 }
2271
2272 if (result_value != 0) {
2273 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2274 TARGET_PRIxADDR, result_value, address + size * (count-1));
2275 if (count > 1) {
2276 LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2277 " and 0x%" TARGET_PRIxADDR " as well, but we "
2278 "didn't check then.)",
2279 address, address + size * (count-2) + size - 1);
2280 }
2281 goto error;
2282 }
2283
2284 scans_delete(scans);
2285 cache_clean(target);
2286 return register_write(target, T0, t0);
2287
2288 error:
2289 scans_delete(scans);
2290 cache_clean(target);
2291 return ERROR_FAIL;
2292 }
2293
2294 static int arch_state(struct target *target)
2295 {
2296 return ERROR_OK;
2297 }
2298
2299 static int init_target(struct command_context *cmd_ctx,
2300 struct target *target)
2301 {
2302 LOG_DEBUG("init");
2303 riscv_info_t *generic_info = (riscv_info_t *)target->arch_info;
2304 generic_info->get_register = get_register;
2305 generic_info->set_register = set_register;
2306 generic_info->read_memory = read_memory;
2307
2308 generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
2309 if (!generic_info->version_specific)
2310 return ERROR_FAIL;
2311
2312 /* Assume 32-bit until we discover the real value in examine(). */
2313 generic_info->xlen[0] = 32;
2314 riscv_init_registers(target);
2315
2316 return ERROR_OK;
2317 }
2318
2319 struct target_type riscv011_target = {
2320 .name = "riscv",
2321
2322 .init_target = init_target,
2323 .deinit_target = deinit_target,
2324 .examine = examine,
2325
2326 /* poll current target status */
2327 .poll = riscv011_poll,
2328
2329 .halt = halt,
2330 .resume = riscv011_resume,
2331 .step = step,
2332
2333 .assert_reset = assert_reset,
2334 .deassert_reset = deassert_reset,
2335
2336 .write_memory = write_memory,
2337
2338 .arch_state = arch_state,
2339 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)