1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2011 by Broadcom Corporation *
5 * Evan Hunter - ehunter@broadcom.com *
6 ***************************************************************************/
13 #include "target/armv7m.h"
14 #include "rtos_standard_stackings.h"
16 static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets
[ARMV7M_NUM_CORE_REGS
] = {
17 { ARMV7M_R0
, 0x20, 32 }, /* r0 */
18 { ARMV7M_R1
, 0x24, 32 }, /* r1 */
19 { ARMV7M_R2
, 0x28, 32 }, /* r2 */
20 { ARMV7M_R3
, 0x2c, 32 }, /* r3 */
21 { ARMV7M_R4
, 0x00, 32 }, /* r4 */
22 { ARMV7M_R5
, 0x04, 32 }, /* r5 */
23 { ARMV7M_R6
, 0x08, 32 }, /* r6 */
24 { ARMV7M_R7
, 0x0c, 32 }, /* r7 */
25 { ARMV7M_R8
, 0x10, 32 }, /* r8 */
26 { ARMV7M_R9
, 0x14, 32 }, /* r9 */
27 { ARMV7M_R10
, 0x18, 32 }, /* r10 */
28 { ARMV7M_R11
, 0x1c, 32 }, /* r11 */
29 { ARMV7M_R12
, 0x30, 32 }, /* r12 */
30 { ARMV7M_R13
, -2, 32 }, /* sp */
31 { ARMV7M_R14
, 0x34, 32 }, /* lr */
32 { ARMV7M_PC
, 0x38, 32 }, /* pc */
33 { ARMV7M_XPSR
, 0x3c, 32 }, /* xPSR */
36 static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets
[] = {
37 { ARMV7M_R0
, 0x24, 32 }, /* r0 */
38 { ARMV7M_R1
, 0x28, 32 }, /* r1 */
39 { ARMV7M_R2
, 0x2c, 32 }, /* r2 */
40 { ARMV7M_R3
, 0x30, 32 }, /* r3 */
41 { ARMV7M_R4
, 0x00, 32 }, /* r4 */
42 { ARMV7M_R5
, 0x04, 32 }, /* r5 */
43 { ARMV7M_R6
, 0x08, 32 }, /* r6 */
44 { ARMV7M_R7
, 0x0c, 32 }, /* r7 */
45 { ARMV7M_R8
, 0x10, 32 }, /* r8 */
46 { ARMV7M_R9
, 0x14, 32 }, /* r9 */
47 { ARMV7M_R10
, 0x18, 32 }, /* r10 */
48 { ARMV7M_R11
, 0x1c, 32 }, /* r11 */
49 { ARMV7M_R12
, 0x34, 32 }, /* r12 */
50 { ARMV7M_R13
, -2, 32 }, /* sp */
51 { ARMV7M_R14
, 0x38, 32 }, /* lr */
52 { ARMV7M_PC
, 0x3c, 32 }, /* pc */
53 { ARMV7M_XPSR
, 0x40, 32 }, /* xPSR */
56 static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets
[] = {
57 { ARMV7M_R0
, 0x64, 32 }, /* r0 */
58 { ARMV7M_R1
, 0x68, 32 }, /* r1 */
59 { ARMV7M_R2
, 0x6c, 32 }, /* r2 */
60 { ARMV7M_R3
, 0x70, 32 }, /* r3 */
61 { ARMV7M_R4
, 0x00, 32 }, /* r4 */
62 { ARMV7M_R5
, 0x04, 32 }, /* r5 */
63 { ARMV7M_R6
, 0x08, 32 }, /* r6 */
64 { ARMV7M_R7
, 0x0c, 32 }, /* r7 */
65 { ARMV7M_R8
, 0x10, 32 }, /* r8 */
66 { ARMV7M_R9
, 0x14, 32 }, /* r9 */
67 { ARMV7M_R10
, 0x18, 32 }, /* r10 */
68 { ARMV7M_R11
, 0x1c, 32 }, /* r11 */
69 { ARMV7M_R12
, 0x74, 32 }, /* r12 */
70 { ARMV7M_R13
, -2, 32 }, /* sp */
71 { ARMV7M_R14
, 0x78, 32 }, /* lr */
72 { ARMV7M_PC
, 0x7c, 32 }, /* pc */
73 { ARMV7M_XPSR
, 0x80, 32 }, /* xPSR */
77 static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets
[] = {
78 { 0, 0x08, 32 }, /* r0 (a1) */
79 { 1, 0x0c, 32 }, /* r1 (a2) */
80 { 2, 0x10, 32 }, /* r2 (a3) */
81 { 3, 0x14, 32 }, /* r3 (a4) */
82 { 4, 0x18, 32 }, /* r4 (v1) */
83 { 5, 0x1c, 32 }, /* r5 (v2) */
84 { 6, 0x20, 32 }, /* r6 (v3) */
85 { 7, 0x24, 32 }, /* r7 (v4) */
86 { 8, 0x28, 32 }, /* r8 (a1) */
87 { 10, 0x2c, 32 }, /* r9 (sb) */
88 { 11, 0x30, 32 }, /* r10 (sl) */
89 { 12, 0x34, 32 }, /* r11 (fp) */
90 { 13, 0x38, 32 }, /* r12 (ip) */
91 { 14, -2, 32 }, /* sp */
92 { 15, 0x3c, 32 }, /* lr */
93 { 16, 0x40, 32 }, /* pc */
94 { 17, -1, 96 }, /* FPA1 */
95 { 18, -1, 96 }, /* FPA2 */
96 { 19, -1, 96 }, /* FPA3 */
97 { 20, -1, 96 }, /* FPA4 */
98 { 21, -1, 96 }, /* FPA5 */
99 { 22, -1, 96 }, /* FPA6 */
100 { 23, -1, 96 }, /* FPA7 */
101 { 24, -1, 96 }, /* FPA8 */
102 { 25, -1, 32 }, /* FPS */
103 { 26, 0x04, 32 }, /* CSPR */
106 static target_addr_t
rtos_generic_stack_align(struct target
*target
,
107 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
108 target_addr_t stack_ptr
, int align
)
110 target_addr_t new_stack_ptr
;
111 target_addr_t aligned_stack_ptr
;
112 new_stack_ptr
= stack_ptr
- stacking
->stack_growth_direction
*
113 stacking
->stack_registers_size
;
114 aligned_stack_ptr
= new_stack_ptr
& ~((target_addr_t
)align
- 1);
115 if (aligned_stack_ptr
!= new_stack_ptr
&&
116 stacking
->stack_growth_direction
== -1) {
117 /* If we have a downward growing stack, the simple alignment code
118 * above results in a wrong result (since it rounds down to nearest
119 * alignment). We want to round up so add an extra align.
121 aligned_stack_ptr
+= (target_addr_t
)align
;
123 return aligned_stack_ptr
;
126 target_addr_t
rtos_generic_stack_align8(struct target
*target
,
127 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
128 target_addr_t stack_ptr
)
130 return rtos_generic_stack_align(target
, stack_data
,
131 stacking
, stack_ptr
, 8);
134 /* The Cortex-M3 will indicate that an alignment adjustment
135 * has been done on the stack by setting bit 9 of the stacked xPSR
136 * register. In this case, we can just add an extra 4 bytes to get
137 * to the program stack. Note that some places in the ARM documentation
138 * make this a little unclear but the padding takes place before the
139 * normal exception stacking - so xPSR is always available at a fixed
142 * Relevant documentation:
143 * Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
144 * Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
145 * Exception Model -> Exception entry and return -> Exception entry
146 * Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
147 * Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
148 * System control block -> Configuration and Control Register (STKALIGN)
150 * This is just a helper function for use in the calculate_process_stack
151 * function for a given architecture/rtos.
153 target_addr_t
rtos_cortex_m_stack_align(struct target
*target
,
154 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
155 target_addr_t stack_ptr
, size_t xpsr_offset
)
157 const uint32_t ALIGN_NEEDED
= (1 << 9);
159 target_addr_t new_stack_ptr
;
161 new_stack_ptr
= stack_ptr
- stacking
->stack_growth_direction
*
162 stacking
->stack_registers_size
;
163 xpsr
= (target
->endianness
== TARGET_LITTLE_ENDIAN
) ?
164 le_to_h_u32(&stack_data
[xpsr_offset
]) :
165 be_to_h_u32(&stack_data
[xpsr_offset
]);
166 if ((xpsr
& ALIGN_NEEDED
) != 0) {
167 LOG_DEBUG("XPSR(0x%08" PRIx32
") indicated stack alignment was necessary\r\n",
169 new_stack_ptr
-= (stacking
->stack_growth_direction
* 4);
171 return new_stack_ptr
;
174 static target_addr_t
rtos_standard_cortex_m3_stack_align(struct target
*target
,
175 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
176 target_addr_t stack_ptr
)
178 const int XPSR_OFFSET
= 0x3c;
179 return rtos_cortex_m_stack_align(target
, stack_data
, stacking
,
180 stack_ptr
, XPSR_OFFSET
);
183 static target_addr_t
rtos_standard_cortex_m4f_stack_align(struct target
*target
,
184 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
185 target_addr_t stack_ptr
)
187 const int XPSR_OFFSET
= 0x40;
188 return rtos_cortex_m_stack_align(target
, stack_data
, stacking
,
189 stack_ptr
, XPSR_OFFSET
);
192 static target_addr_t
rtos_standard_cortex_m4f_fpu_stack_align(struct target
*target
,
193 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
194 target_addr_t stack_ptr
)
196 const int XPSR_OFFSET
= 0x80;
197 return rtos_cortex_m_stack_align(target
, stack_data
, stacking
,
198 stack_ptr
, XPSR_OFFSET
);
202 const struct rtos_register_stacking rtos_standard_cortex_m3_stacking
= {
203 .stack_registers_size
= 0x40,
204 .stack_growth_direction
= -1,
205 .num_output_registers
= ARMV7M_NUM_CORE_REGS
,
206 .calculate_process_stack
= rtos_standard_cortex_m3_stack_align
,
207 .register_offsets
= rtos_standard_cortex_m3_stack_offsets
210 const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking
= {
211 .stack_registers_size
= 0x44,
212 .stack_growth_direction
= -1,
213 .num_output_registers
= ARMV7M_NUM_CORE_REGS
,
214 .calculate_process_stack
= rtos_standard_cortex_m4f_stack_align
,
215 .register_offsets
= rtos_standard_cortex_m4f_stack_offsets
218 const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking
= {
219 .stack_registers_size
= 0xcc,
220 .stack_growth_direction
= -1,
221 .num_output_registers
= ARMV7M_NUM_CORE_REGS
,
222 .calculate_process_stack
= rtos_standard_cortex_m4f_fpu_stack_align
,
223 .register_offsets
= rtos_standard_cortex_m4f_fpu_stack_offsets
226 const struct rtos_register_stacking rtos_standard_cortex_r4_stacking
= {
227 .stack_registers_size
= 0x48,
228 .stack_growth_direction
= -1,
229 .num_output_registers
= 26,
230 .calculate_process_stack
= rtos_generic_stack_align8
,
231 .register_offsets
= rtos_standard_cortex_r4_stack_offsets
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