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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / stm32h7x.c
1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17 #ifdef HAVE_CONFIG_H
18 #include "config.h"
19 #endif
20
21 #include "imp.h"
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
25
26
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
30
31 /* RM 433 */
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
37 #define FLASH_CR 0x0C
38 #define FLASH_SR 0x10
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
46
47
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
59
60 /* FLASH_SR register bits */
61 #define FLASH_BSY (1 << 0) /* Operation in progress */
62 #define FLASH_QW (1 << 2) /* Operation queue in progress */
63 #define FLASH_WRPERR (1 << 17) /* Write protection error */
64 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
65 #define FLASH_STRBERR (1 << 19) /* Strobe error */
66 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
67 #define FLASH_OPERR (1 << 22) /* Operation error */
68 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
69 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
72
73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
74 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
75
76 /* FLASH_OPTCR register bits */
77 #define OPT_LOCK (1 << 0)
78 #define OPT_START (1 << 1)
79
80 /* FLASH_OPTSR register bits */
81 #define OPT_BSY (1 << 0)
82 #define OPT_RDP_POS 8
83 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
84 #define OPT_OPTCHANGEERR (1 << 30)
85
86 /* FLASH_OPTCCR register bits */
87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
88
89 /* register unlock keys */
90 #define KEY1 0x45670123
91 #define KEY2 0xCDEF89AB
92
93 /* option register unlock key */
94 #define OPTKEY1 0x08192A3B
95 #define OPTKEY2 0x4C5D6E7F
96
97 #define DBGMCU_IDCODE_REGISTER 0x5C001000
98 #define FLASH_BANK0_ADDRESS 0x08000000
99 #define FLASH_BANK1_ADDRESS 0x08100000
100 #define FLASH_REG_BASE_B0 0x52002000
101 #define FLASH_REG_BASE_B1 0x52002100
102
103 struct stm32h7x_rev {
104 uint16_t rev;
105 const char *str;
106 };
107
108 /* stm32h7x_part_info permits the store each device information and specificities.
109 * the default unit is byte unless the suffix '_kb' is used. */
110
111 struct stm32h7x_part_info {
112 uint16_t id;
113 const char *device_str;
114 const struct stm32h7x_rev *revs;
115 size_t num_revs;
116 unsigned int page_size_kb;
117 unsigned int block_size; /* flash write word size in bytes */
118 uint16_t max_flash_size_kb;
119 bool has_dual_bank;
120 uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
121 uint32_t fsize_addr; /* Location of FSIZE register */
122 uint32_t wps_group_size; /* write protection group sectors' count */
123 uint32_t wps_mask;
124 /* function to compute flash_cr register values */
125 uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
126 };
127
128 struct stm32h7x_flash_bank {
129 bool probed;
130 uint32_t idcode;
131 uint32_t user_bank_size;
132 uint32_t flash_regs_base; /* Address of flash reg controller */
133 const struct stm32h7x_part_info *part_info;
134 };
135
136 enum stm32h7x_opt_rdp {
137 OPT_RDP_L0 = 0xaa,
138 OPT_RDP_L1 = 0x00,
139 OPT_RDP_L2 = 0xcc
140 };
141
142 static const struct stm32h7x_rev stm32_450_revs[] = {
143 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
144 };
145
146 static const struct stm32h7x_rev stm32_480_revs[] = {
147 { 0x1000, "A"},
148 };
149
150 static const struct stm32h7x_rev stm32_483_revs[] = {
151 { 0x1000, "A" }, { 0x1001, "Z" },
152 };
153
154 static uint32_t stm32x_compute_flash_cr_450_483(uint32_t cmd, int snb)
155 {
156 return cmd | (snb << 8);
157 }
158
159 static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
160 {
161 /* save FW and START bits, to be right shifted by 2 bits later */
162 const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
163
164 /* mask parallelism (ignored), FW and START bits */
165 cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
166
167 return cmd | (tmp >> 2) | (snb << 6);
168 }
169
170 static const struct stm32h7x_part_info stm32h7x_parts[] = {
171 {
172 .id = 0x450,
173 .revs = stm32_450_revs,
174 .num_revs = ARRAY_SIZE(stm32_450_revs),
175 .device_str = "STM32H74x/75x",
176 .page_size_kb = 128,
177 .block_size = 32,
178 .max_flash_size_kb = 2048,
179 .max_bank_size_kb = 1024,
180 .has_dual_bank = true,
181 .fsize_addr = 0x1FF1E880,
182 .wps_group_size = 1,
183 .wps_mask = 0xFF,
184 .compute_flash_cr = stm32x_compute_flash_cr_450_483,
185 },
186 {
187 .id = 0x480,
188 .revs = stm32_480_revs,
189 .num_revs = ARRAY_SIZE(stm32_480_revs),
190 .device_str = "STM32H7Ax/7Bx",
191 .page_size_kb = 8,
192 .block_size = 16,
193 .max_flash_size_kb = 2048,
194 .max_bank_size_kb = 1024,
195 .has_dual_bank = true,
196 .fsize_addr = 0x08FFF80C,
197 .wps_group_size = 4,
198 .wps_mask = 0xFFFFFFFF,
199 .compute_flash_cr = stm32x_compute_flash_cr_480,
200 },
201 {
202 .id = 0x483,
203 .revs = stm32_483_revs,
204 .num_revs = ARRAY_SIZE(stm32_483_revs),
205 .device_str = "STM32H72x/73x",
206 .page_size_kb = 128,
207 .block_size = 32,
208 .max_flash_size_kb = 1024,
209 .max_bank_size_kb = 1024,
210 .has_dual_bank = false,
211 .fsize_addr = 0x1FF1E880,
212 .wps_group_size = 1,
213 .wps_mask = 0xFF,
214 .compute_flash_cr = stm32x_compute_flash_cr_450_483,
215 },
216 };
217
218 /* flash bank stm32x <base> <size> 0 0 <target#> */
219
220 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
221 {
222 struct stm32h7x_flash_bank *stm32x_info;
223
224 if (CMD_ARGC < 6)
225 return ERROR_COMMAND_SYNTAX_ERROR;
226
227 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
228 bank->driver_priv = stm32x_info;
229
230 stm32x_info->probed = false;
231 stm32x_info->user_bank_size = bank->size;
232
233 return ERROR_OK;
234 }
235
236 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
237 {
238 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
239 return reg_offset + stm32x_info->flash_regs_base;
240 }
241
242 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
243 {
244 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
245 int retval = target_read_u32(bank->target, reg_addr, value);
246
247 if (retval != ERROR_OK)
248 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
249
250 return retval;
251 }
252
253 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
254 {
255 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
256 int retval = target_write_u32(bank->target, reg_addr, value);
257
258 if (retval != ERROR_OK)
259 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
260
261 return retval;
262 }
263
264 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
265 {
266 return stm32x_read_flash_reg(bank, FLASH_SR, status);
267 }
268
269 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
270 {
271 uint32_t status;
272 int retval;
273
274 /* wait for flash operations completion */
275 for (;;) {
276 retval = stm32x_get_flash_status(bank, &status);
277 if (retval != ERROR_OK)
278 return retval;
279
280 if ((status & FLASH_QW) == 0)
281 break;
282
283 if (timeout-- <= 0) {
284 LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32, status);
285 return ERROR_FAIL;
286 }
287 alive_sleep(1);
288 }
289
290 if (status & FLASH_WRPERR) {
291 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
292 retval = ERROR_FAIL;
293 }
294
295 /* Clear error + EOP flags but report errors */
296 if (status & FLASH_ERROR) {
297 if (retval == ERROR_OK)
298 retval = ERROR_FAIL;
299 /* If this operation fails, we ignore it and report the original retval */
300 stm32x_write_flash_reg(bank, FLASH_CCR, status);
301 }
302 return retval;
303 }
304
305 static int stm32x_unlock_reg(struct flash_bank *bank)
306 {
307 uint32_t ctrl;
308
309 /* first check if not already unlocked
310 * otherwise writing on FLASH_KEYR will fail
311 */
312 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
313 if (retval != ERROR_OK)
314 return retval;
315
316 if ((ctrl & FLASH_LOCK) == 0)
317 return ERROR_OK;
318
319 /* unlock flash registers for bank */
320 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
321 if (retval != ERROR_OK)
322 return retval;
323
324 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
325 if (retval != ERROR_OK)
326 return retval;
327
328 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
329 if (retval != ERROR_OK)
330 return retval;
331
332 if (ctrl & FLASH_LOCK) {
333 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: 0x%" PRIx32, ctrl);
334 return ERROR_TARGET_FAILURE;
335 }
336 return ERROR_OK;
337 }
338
339 static int stm32x_unlock_option_reg(struct flash_bank *bank)
340 {
341 uint32_t ctrl;
342
343 int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
344 if (retval != ERROR_OK)
345 return retval;
346
347 if ((ctrl & OPT_LOCK) == 0)
348 return ERROR_OK;
349
350 /* unlock option registers */
351 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
352 if (retval != ERROR_OK)
353 return retval;
354
355 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
356 if (retval != ERROR_OK)
357 return retval;
358
359 retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
360 if (retval != ERROR_OK)
361 return retval;
362
363 if (ctrl & OPT_LOCK) {
364 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
365 return ERROR_TARGET_FAILURE;
366 }
367
368 return ERROR_OK;
369 }
370
371 static inline int stm32x_lock_reg(struct flash_bank *bank)
372 {
373 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
374 }
375
376 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
377 {
378 return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
379 }
380
381 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
382 {
383 int retval, retval2;
384
385 /* unlock option bytes for modification */
386 retval = stm32x_unlock_option_reg(bank);
387 if (retval != ERROR_OK)
388 goto flash_options_lock;
389
390 /* write option bytes */
391 retval = stm32x_write_flash_reg(bank, reg_offset, value);
392 if (retval != ERROR_OK)
393 goto flash_options_lock;
394
395 /* Remove OPT error flag before programming */
396 retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
397 if (retval != ERROR_OK)
398 goto flash_options_lock;
399
400 /* start programming cycle */
401 retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
402 if (retval != ERROR_OK)
403 goto flash_options_lock;
404
405 /* wait for completion */
406 int timeout = FLASH_ERASE_TIMEOUT;
407 uint32_t status;
408 for (;;) {
409 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
410 if (retval != ERROR_OK) {
411 LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
412 goto flash_options_lock;
413 }
414 if ((status & OPT_BSY) == 0)
415 break;
416
417 if (timeout-- <= 0) {
418 LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32, status);
419 retval = ERROR_FAIL;
420 goto flash_options_lock;
421 }
422 alive_sleep(1);
423 }
424
425 /* check for failure */
426 if (status & OPT_OPTCHANGEERR) {
427 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
428 retval = ERROR_FLASH_OPERATION_FAILED;
429 }
430
431 flash_options_lock:
432 retval2 = stm32x_lock_option_reg(bank);
433 if (retval2 != ERROR_OK)
434 LOG_ERROR("error during the lock of flash options");
435
436 return (retval == ERROR_OK) ? retval2 : retval;
437 }
438
439 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
440 {
441 uint32_t data;
442
443 int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
444 if (retval != ERROR_OK)
445 return retval;
446
447 data = (data & ~mask) | (value & mask);
448
449 return stm32x_write_option(bank, reg_offset, data);
450 }
451
452 static int stm32x_protect_check(struct flash_bank *bank)
453 {
454 uint32_t protection;
455
456 /* read 'write protection' settings */
457 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
458 if (retval != ERROR_OK) {
459 LOG_DEBUG("unable to read WPSN_CUR register");
460 return retval;
461 }
462
463 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
464 bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
465
466 return ERROR_OK;
467 }
468
469 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
470 unsigned int last)
471 {
472 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
473 int retval, retval2;
474
475 assert(first < bank->num_sectors);
476 assert(last < bank->num_sectors);
477
478 if (bank->target->state != TARGET_HALTED)
479 return ERROR_TARGET_NOT_HALTED;
480
481 retval = stm32x_unlock_reg(bank);
482 if (retval != ERROR_OK)
483 goto flash_lock;
484
485 /*
486 Sector Erase
487 To erase a sector, follow the procedure below:
488 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
489 FLASH_SR register
490 2. Set the SER bit and select the sector
491 you wish to erase (SNB) in the FLASH_CR register
492 3. Set the STRT bit in the FLASH_CR register
493 4. Wait for flash operations completion
494 */
495 for (unsigned int i = first; i <= last; i++) {
496 LOG_DEBUG("erase sector %u", i);
497 retval = stm32x_write_flash_reg(bank, FLASH_CR,
498 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
499 if (retval != ERROR_OK) {
500 LOG_ERROR("Error erase sector %u", i);
501 goto flash_lock;
502 }
503 retval = stm32x_write_flash_reg(bank, FLASH_CR,
504 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
505 if (retval != ERROR_OK) {
506 LOG_ERROR("Error erase sector %u", i);
507 goto flash_lock;
508 }
509 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
510
511 if (retval != ERROR_OK) {
512 LOG_ERROR("erase time-out or operation error sector %u", i);
513 goto flash_lock;
514 }
515 bank->sectors[i].is_erased = 1;
516 }
517
518 flash_lock:
519 retval2 = stm32x_lock_reg(bank);
520 if (retval2 != ERROR_OK)
521 LOG_ERROR("error during the lock of flash");
522
523 return (retval == ERROR_OK) ? retval2 : retval;
524 }
525
526 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
527 unsigned int last)
528 {
529 struct target *target = bank->target;
530 uint32_t protection;
531
532 if (target->state != TARGET_HALTED) {
533 LOG_ERROR("Target not halted");
534 return ERROR_TARGET_NOT_HALTED;
535 }
536
537 /* read 'write protection' settings */
538 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
539 if (retval != ERROR_OK) {
540 LOG_DEBUG("unable to read WPSN_CUR register");
541 return retval;
542 }
543
544 for (unsigned int i = first; i <= last; i++) {
545 if (set)
546 protection &= ~(1 << i);
547 else
548 protection |= (1 << i);
549 }
550
551 /* apply WRPSN mask */
552 protection &= 0xff;
553
554 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
555
556 /* apply new option value */
557 return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
558 }
559
560 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
561 uint32_t offset, uint32_t count)
562 {
563 struct target *target = bank->target;
564 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
565 /*
566 * If the size of the data part of the buffer is not a multiple of .block_size, we get
567 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
568 */
569 uint32_t data_size = 512 * stm32x_info->part_info->block_size;
570 uint32_t buffer_size = 8 + data_size;
571 struct working_area *write_algorithm;
572 struct working_area *source;
573 uint32_t address = bank->base + offset;
574 struct reg_param reg_params[6];
575 struct armv7m_algorithm armv7m_info;
576 int retval = ERROR_OK;
577
578 static const uint8_t stm32x_flash_write_code[] = {
579 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
580 };
581
582 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
583 &write_algorithm) != ERROR_OK) {
584 LOG_WARNING("no working area available, can't do block memory writes");
585 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
586 }
587
588 retval = target_write_buffer(target, write_algorithm->address,
589 sizeof(stm32x_flash_write_code),
590 stm32x_flash_write_code);
591 if (retval != ERROR_OK) {
592 target_free_working_area(target, write_algorithm);
593 return retval;
594 }
595
596 /* memory buffer */
597 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
598 data_size /= 2;
599 buffer_size = 8 + data_size;
600 if (data_size <= 256) {
601 /* we already allocated the writing code, but failed to get a
602 * buffer, free the algorithm */
603 target_free_working_area(target, write_algorithm);
604
605 LOG_WARNING("no large enough working area available, can't do block memory writes");
606 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
607 }
608 }
609
610 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
611
612 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
613 armv7m_info.core_mode = ARM_MODE_THREAD;
614
615 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
616 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
617 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
618 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
619 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
620 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
621
622 buf_set_u32(reg_params[0].value, 0, 32, source->address);
623 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
624 buf_set_u32(reg_params[2].value, 0, 32, address);
625 buf_set_u32(reg_params[3].value, 0, 32, count);
626 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
627 buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
628
629 retval = target_run_flash_async_algorithm(target,
630 buffer,
631 count,
632 stm32x_info->part_info->block_size,
633 0, NULL,
634 ARRAY_SIZE(reg_params), reg_params,
635 source->address, source->size,
636 write_algorithm->address, 0,
637 &armv7m_info);
638
639 if (retval == ERROR_FLASH_OPERATION_FAILED) {
640 LOG_ERROR("error executing stm32h7x flash write algorithm");
641
642 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
643
644 if (flash_sr & FLASH_WRPERR)
645 LOG_ERROR("flash memory write protected");
646
647 if ((flash_sr & FLASH_ERROR) != 0) {
648 LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
649 /* Clear error + EOP flags but report errors */
650 stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
651 retval = ERROR_FAIL;
652 }
653 }
654
655 target_free_working_area(target, source);
656 target_free_working_area(target, write_algorithm);
657
658 destroy_reg_param(&reg_params[0]);
659 destroy_reg_param(&reg_params[1]);
660 destroy_reg_param(&reg_params[2]);
661 destroy_reg_param(&reg_params[3]);
662 destroy_reg_param(&reg_params[4]);
663 destroy_reg_param(&reg_params[5]);
664 return retval;
665 }
666
667 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
668 uint32_t offset, uint32_t count)
669 {
670 struct target *target = bank->target;
671 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
672 uint32_t address = bank->base + offset;
673 int retval, retval2;
674
675 if (bank->target->state != TARGET_HALTED) {
676 LOG_ERROR("Target not halted");
677 return ERROR_TARGET_NOT_HALTED;
678 }
679
680 /* should be enforced via bank->write_start_alignment */
681 assert(!(offset % stm32x_info->part_info->block_size));
682
683 /* should be enforced via bank->write_end_alignment */
684 assert(!(count % stm32x_info->part_info->block_size));
685
686 retval = stm32x_unlock_reg(bank);
687 if (retval != ERROR_OK)
688 goto flash_lock;
689
690 uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
691
692 /* multiple words (n * .block_size) to be programmed in block */
693 if (blocks_remaining) {
694 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
695 if (retval != ERROR_OK) {
696 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
697 /* if block write failed (no sufficient working area),
698 * we use normal (slow) dword accesses */
699 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
700 }
701 } else {
702 buffer += blocks_remaining * stm32x_info->part_info->block_size;
703 address += blocks_remaining * stm32x_info->part_info->block_size;
704 blocks_remaining = 0;
705 }
706 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
707 goto flash_lock;
708 }
709
710 /*
711 Standard programming
712 The Flash memory programming sequence is as follows:
713 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
714 FLASH_SR register.
715 2. Set the PG bit in the FLASH_CR register
716 3. 8 x Word access (or Force Write FW)
717 4. Wait for flash operations completion
718 */
719 while (blocks_remaining > 0) {
720 retval = stm32x_write_flash_reg(bank, FLASH_CR,
721 stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
722 if (retval != ERROR_OK)
723 goto flash_lock;
724
725 retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
726 if (retval != ERROR_OK)
727 goto flash_lock;
728
729 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
730 if (retval != ERROR_OK)
731 goto flash_lock;
732
733 buffer += stm32x_info->part_info->block_size;
734 address += stm32x_info->part_info->block_size;
735 blocks_remaining--;
736 }
737
738 flash_lock:
739 retval2 = stm32x_lock_reg(bank);
740 if (retval2 != ERROR_OK)
741 LOG_ERROR("error during the lock of flash");
742
743 return (retval == ERROR_OK) ? retval2 : retval;
744 }
745
746 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
747 {
748 /* read stm32 device id register */
749 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
750 if (retval != ERROR_OK)
751 return retval;
752 return ERROR_OK;
753 }
754
755 static int stm32x_probe(struct flash_bank *bank)
756 {
757 struct target *target = bank->target;
758 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
759 uint16_t flash_size_in_kb;
760 uint32_t device_id;
761
762 stm32x_info->probed = false;
763 stm32x_info->part_info = NULL;
764
765 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
766 if (retval != ERROR_OK)
767 return retval;
768
769 LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
770
771 device_id = stm32x_info->idcode & 0xfff;
772
773 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
774 if (device_id == stm32h7x_parts[n].id)
775 stm32x_info->part_info = &stm32h7x_parts[n];
776 }
777 if (!stm32x_info->part_info) {
778 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
779 return ERROR_FAIL;
780 } else {
781 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
782 }
783
784 /* update the address of controller */
785 if (bank->base == FLASH_BANK0_ADDRESS)
786 stm32x_info->flash_regs_base = FLASH_REG_BASE_B0;
787 else if (bank->base == FLASH_BANK1_ADDRESS)
788 stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
789 else {
790 LOG_WARNING("Flash register base not defined for bank %u", bank->bank_number);
791 return ERROR_FAIL;
792 }
793 LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
794
795 /* get flash size from target */
796 retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
797 if (retval != ERROR_OK) {
798 /* read error when device has invalid value, set max flash size */
799 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
800 } else
801 LOG_INFO("flash size probed value %" PRIu16, flash_size_in_kb);
802
803
804
805
806 /* setup bank size */
807 const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
808 const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
809 bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
810
811 switch (device_id) {
812 case 0x450:
813 case 0x480:
814 /* For STM32H74x/75x and STM32H7Ax/Bx
815 * - STM32H7xxxI devices contains dual bank, 1 Mbyte each
816 * - STM32H7xxxG devices contains dual bank, 512 Kbyte each
817 * - STM32H7xxxB devices contains single bank, 128 Kbyte
818 * - the second bank starts always from 0x08100000
819 */
820 if (flash_size_in_kb == 128)
821 has_dual_bank = false;
822 else
823 /* flash size is 2M or 1M */
824 flash_size_in_kb /= 2;
825 break;
826 case 0x483:
827 break;
828 default:
829 LOG_ERROR("unsupported device");
830 return ERROR_FAIL;
831 }
832
833 if (has_dual_bank) {
834 LOG_INFO("STM32H7 flash has dual banks");
835 if (bank->base != bank1_base && bank->base != bank2_base) {
836 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
837 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
838 bank->base, bank1_base, bank2_base);
839 return ERROR_FAIL;
840 }
841 } else {
842 LOG_INFO("STM32H7 flash has a single bank");
843 if (bank->base == bank2_base) {
844 LOG_ERROR("this device has a single bank only");
845 return ERROR_FAIL;
846 } else if (bank->base != bank1_base) {
847 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
848 TARGET_ADDR_FMT " but should be 0x%" PRIx32,
849 bank->base, bank1_base);
850 return ERROR_FAIL;
851 }
852 }
853
854 LOG_INFO("Bank (%u) size is %" PRIu16 " kb, base address is " TARGET_ADDR_FMT,
855 bank->bank_number, flash_size_in_kb, bank->base);
856
857 /* if the user sets the size manually then ignore the probed value
858 * this allows us to work around devices that have an invalid flash size register value */
859 if (stm32x_info->user_bank_size) {
860 LOG_INFO("ignoring flash probed value, using configured bank size");
861 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
862 } else if (flash_size_in_kb == 0xffff) {
863 /* die flash size */
864 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
865 }
866
867 /* did we assign flash size? */
868 assert(flash_size_in_kb != 0xffff);
869 bank->size = flash_size_in_kb * 1024;
870 bank->write_start_alignment = stm32x_info->part_info->block_size;
871 bank->write_end_alignment = stm32x_info->part_info->block_size;
872
873 /* setup sectors */
874 bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
875 assert(bank->num_sectors > 0);
876
877 free(bank->sectors);
878
879 bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
880 bank->num_sectors);
881
882 if (bank->sectors == NULL) {
883 LOG_ERROR("failed to allocate bank sectors");
884 return ERROR_FAIL;
885 }
886
887 /* setup protection blocks */
888 const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
889 assert(bank->num_sectors % wpsn == 0);
890
891 bank->num_prot_blocks = bank->num_sectors / wpsn;
892 assert(bank->num_prot_blocks > 0);
893
894 free(bank->prot_blocks);
895
896 bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
897 bank->num_prot_blocks);
898
899 if (bank->prot_blocks == NULL) {
900 LOG_ERROR("failed to allocate bank prot_block");
901 return ERROR_FAIL;
902 }
903
904 stm32x_info->probed = true;
905 return ERROR_OK;
906 }
907
908 static int stm32x_auto_probe(struct flash_bank *bank)
909 {
910 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
911
912 if (stm32x_info->probed)
913 return ERROR_OK;
914
915 return stm32x_probe(bank);
916 }
917
918 /* This method must return a string displaying information about the bank */
919 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
920 {
921 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
922 const struct stm32h7x_part_info *info = stm32x_info->part_info;
923
924 if (!stm32x_info->probed) {
925 int retval = stm32x_probe(bank);
926 if (retval != ERROR_OK) {
927 snprintf(buf, buf_size, "Unable to find bank information.");
928 return retval;
929 }
930 }
931
932 if (info) {
933 const char *rev_str = NULL;
934 uint16_t rev_id = stm32x_info->idcode >> 16;
935
936 for (unsigned int i = 0; i < info->num_revs; i++)
937 if (rev_id == info->revs[i].rev)
938 rev_str = info->revs[i].str;
939
940 if (rev_str != NULL) {
941 snprintf(buf, buf_size, "%s - Rev: %s",
942 stm32x_info->part_info->device_str, rev_str);
943 } else {
944 snprintf(buf, buf_size,
945 "%s - Rev: unknown (0x%04" PRIx16 ")",
946 stm32x_info->part_info->device_str, rev_id);
947 }
948 } else {
949 snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
950 return ERROR_FAIL;
951 }
952 return ERROR_OK;
953 }
954
955 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
956 {
957 struct target *target = bank->target;
958 uint32_t optsr, cur_rdp;
959 int retval;
960
961 if (target->state != TARGET_HALTED) {
962 LOG_ERROR("Target not halted");
963 return ERROR_TARGET_NOT_HALTED;
964 }
965
966 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
967
968 if (retval != ERROR_OK) {
969 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
970 return retval;
971 }
972
973 /* get current RDP, and check if there is a change */
974 cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
975 if (new_rdp == cur_rdp) {
976 LOG_INFO("the requested RDP value is already programmed");
977 return ERROR_OK;
978 }
979
980 switch (new_rdp) {
981 case OPT_RDP_L0:
982 LOG_WARNING("unlocking the entire flash device");
983 break;
984 case OPT_RDP_L1:
985 LOG_WARNING("locking the entire flash device");
986 break;
987 case OPT_RDP_L2:
988 LOG_WARNING("locking the entire flash device, irreversible");
989 break;
990 }
991
992 /* apply new RDP */
993 optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
994
995 /* apply new option value */
996 return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
997 }
998
999 COMMAND_HANDLER(stm32x_handle_lock_command)
1000 {
1001 if (CMD_ARGC < 1)
1002 return ERROR_COMMAND_SYNTAX_ERROR;
1003
1004 struct flash_bank *bank;
1005 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1006 if (ERROR_OK != retval)
1007 return retval;
1008
1009 retval = stm32x_set_rdp(bank, OPT_RDP_L1);
1010
1011 if (retval != ERROR_OK)
1012 command_print(CMD, "%s failed to lock device", bank->driver->name);
1013 else
1014 command_print(CMD, "%s locked", bank->driver->name);
1015
1016 return retval;
1017 }
1018
1019 COMMAND_HANDLER(stm32x_handle_unlock_command)
1020 {
1021 if (CMD_ARGC < 1)
1022 return ERROR_COMMAND_SYNTAX_ERROR;
1023
1024 struct flash_bank *bank;
1025 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1026 if (ERROR_OK != retval)
1027 return retval;
1028
1029 retval = stm32x_set_rdp(bank, OPT_RDP_L0);
1030
1031 if (retval != ERROR_OK)
1032 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1033 else
1034 command_print(CMD, "%s unlocked", bank->driver->name);
1035
1036 return retval;
1037 }
1038
1039 static int stm32x_mass_erase(struct flash_bank *bank)
1040 {
1041 int retval, retval2;
1042 struct target *target = bank->target;
1043 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
1044
1045 if (target->state != TARGET_HALTED) {
1046 LOG_ERROR("Target not halted");
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 retval = stm32x_unlock_reg(bank);
1051 if (retval != ERROR_OK)
1052 goto flash_lock;
1053
1054 /* mass erase flash memory bank */
1055 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1056 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
1057 if (retval != ERROR_OK)
1058 goto flash_lock;
1059
1060 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1061 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
1062 if (retval != ERROR_OK)
1063 goto flash_lock;
1064
1065 retval = stm32x_wait_flash_op_queue(bank, 30000);
1066 if (retval != ERROR_OK)
1067 goto flash_lock;
1068
1069 flash_lock:
1070 retval2 = stm32x_lock_reg(bank);
1071 if (retval2 != ERROR_OK)
1072 LOG_ERROR("error during the lock of flash");
1073
1074 return (retval == ERROR_OK) ? retval2 : retval;
1075 }
1076
1077 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1078 {
1079 if (CMD_ARGC < 1) {
1080 command_print(CMD, "stm32h7x mass_erase <bank>");
1081 return ERROR_COMMAND_SYNTAX_ERROR;
1082 }
1083
1084 struct flash_bank *bank;
1085 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1086 if (ERROR_OK != retval)
1087 return retval;
1088
1089 retval = stm32x_mass_erase(bank);
1090 if (retval == ERROR_OK) {
1091 /* set all sectors as erased */
1092 for (unsigned int i = 0; i < bank->num_sectors; i++)
1093 bank->sectors[i].is_erased = 1;
1094
1095 command_print(CMD, "stm32h7x mass erase complete");
1096 } else {
1097 command_print(CMD, "stm32h7x mass erase failed");
1098 }
1099
1100 return retval;
1101 }
1102
1103 COMMAND_HANDLER(stm32x_handle_option_read_command)
1104 {
1105 if (CMD_ARGC < 2) {
1106 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1107 return ERROR_COMMAND_SYNTAX_ERROR;
1108 }
1109
1110 struct flash_bank *bank;
1111 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1112 if (ERROR_OK != retval)
1113 return retval;
1114
1115 uint32_t reg_offset, value;
1116
1117 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1118 retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1119 if (ERROR_OK != retval)
1120 return retval;
1121
1122 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
1123 stm32x_get_flash_reg(bank, reg_offset), value);
1124
1125 return retval;
1126 }
1127
1128 COMMAND_HANDLER(stm32x_handle_option_write_command)
1129 {
1130 if (CMD_ARGC < 3) {
1131 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1132 return ERROR_COMMAND_SYNTAX_ERROR;
1133 }
1134
1135 struct flash_bank *bank;
1136 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1137 if (ERROR_OK != retval)
1138 return retval;
1139
1140 uint32_t reg_offset, value, mask = 0xffffffff;
1141
1142 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1143 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1144 if (CMD_ARGC > 3)
1145 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1146
1147 return stm32x_modify_option(bank, reg_offset, value, mask);
1148 }
1149
1150 static const struct command_registration stm32x_exec_command_handlers[] = {
1151 {
1152 .name = "lock",
1153 .handler = stm32x_handle_lock_command,
1154 .mode = COMMAND_EXEC,
1155 .usage = "bank_id",
1156 .help = "Lock entire flash device.",
1157 },
1158 {
1159 .name = "unlock",
1160 .handler = stm32x_handle_unlock_command,
1161 .mode = COMMAND_EXEC,
1162 .usage = "bank_id",
1163 .help = "Unlock entire protected flash device.",
1164 },
1165 {
1166 .name = "mass_erase",
1167 .handler = stm32x_handle_mass_erase_command,
1168 .mode = COMMAND_EXEC,
1169 .usage = "bank_id",
1170 .help = "Erase entire flash device.",
1171 },
1172 {
1173 .name = "option_read",
1174 .handler = stm32x_handle_option_read_command,
1175 .mode = COMMAND_EXEC,
1176 .usage = "bank_id reg_offset",
1177 .help = "Read and display device option bytes.",
1178 },
1179 {
1180 .name = "option_write",
1181 .handler = stm32x_handle_option_write_command,
1182 .mode = COMMAND_EXEC,
1183 .usage = "bank_id reg_offset value [mask]",
1184 .help = "Write device option bit fields with provided value.",
1185 },
1186 COMMAND_REGISTRATION_DONE
1187 };
1188
1189 static const struct command_registration stm32x_command_handlers[] = {
1190 {
1191 .name = "stm32h7x",
1192 .mode = COMMAND_ANY,
1193 .help = "stm32h7x flash command group",
1194 .usage = "",
1195 .chain = stm32x_exec_command_handlers,
1196 },
1197 COMMAND_REGISTRATION_DONE
1198 };
1199
1200 const struct flash_driver stm32h7x_flash = {
1201 .name = "stm32h7x",
1202 .commands = stm32x_command_handlers,
1203 .flash_bank_command = stm32x_flash_bank_command,
1204 .erase = stm32x_erase,
1205 .protect = stm32x_protect,
1206 .write = stm32x_write,
1207 .read = default_flash_read,
1208 .probe = stm32x_probe,
1209 .auto_probe = stm32x_auto_probe,
1210 .erase_check = default_flash_blank_check,
1211 .protect_check = stm32x_protect_check,
1212 .info = stm32x_get_info,
1213 .free_driver_priv = default_flash_free_driver_priv,
1214 };
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