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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / stm32f2x.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 * *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
9 * *
10 * Copyright (C) 2011 Øyvind Harboe *
11 * oyvind.harboe@zylin.com *
12 ***************************************************************************/
13
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17
18 #include "imp.h"
19 #include <helper/binarybuffer.h>
20 #include <target/algorithm.h>
21 #include <target/cortex_m.h>
22
23 /* Regarding performance:
24 *
25 * Short story - it might be best to leave the performance at
26 * current levels.
27 *
28 * You may see a jump in speed if you change to using
29 * 32bit words for the block programming.
30 *
31 * Its a shame you cannot use the double word as its
32 * even faster - but you require external VPP for that mode.
33 *
34 * Having said all that 16bit writes give us the widest vdd
35 * operating range, so may be worth adding a note to that effect.
36 *
37 */
38
39 /* Danger!!!! The STM32F1x and STM32F2x series actually have
40 * quite different flash controllers.
41 *
42 * What's more scary is that the names of the registers and their
43 * addresses are the same, but the actual bits and what they do are
44 * can be very different.
45 *
46 * To reduce testing complexity and dangers of regressions,
47 * a separate file is used for stm32fx2x.
48 *
49 * Sector sizes in kiBytes:
50 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
51 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
52 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
53 * 1 MiByte STM32F42x/43x part with DB1M Option set:
54 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
55 *
56 * STM32F7[2|3]
57 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
58 *
59 * STM32F7[4|5]
60 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
61 *
62 * STM32F7[6|7]
63 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
64 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
65 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
66 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
67 *
68 * Protection size is sector size.
69 *
70 * Tested with STM3220F-EVAL board.
71 *
72 * STM32F4xx series for reference.
73 *
74 * RM0090
75 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
76 *
77 * PM0059
78 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
79 * PROGRAMMING_MANUAL/CD00233952.pdf
80 *
81 * STM32F7xx series for reference.
82 *
83 * RM0385
84 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
85 *
86 * RM0410
87 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
88 *
89 * RM0430
90 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
91 *
92 * RM0431
93 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
94 *
95 * STM32F1x series - notice that this code was copy, pasted and knocked
96 * into a stm32f2x driver, so in case something has been converted or
97 * bugs haven't been fixed, here are the original manuals:
98 *
99 * RM0008 - Reference manual
100 *
101 * RM0042, the Flash programming manual for low-, medium- high-density and
102 * connectivity line STM32F10x devices
103 *
104 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
105 *
106 */
107
108 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
109 #define FLASH_ERASE_TIMEOUT 10000
110 #define FLASH_WRITE_TIMEOUT 5
111
112 /* Mass erase time can be as high as 32 s in x8 mode. */
113 #define FLASH_MASS_ERASE_TIMEOUT 33000
114
115 #define FLASH_BANK_BASE 0x80000000
116
117 #define STM32F2_OTP_SIZE 512
118 #define STM32F2_OTP_SECTOR_SIZE 32
119 #define STM32F2_OTP_BANK_BASE 0x1fff7800
120 #define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
121
122 /* see RM0410 section 3.6 "One-time programmable bytes" */
123 #define STM32F7_OTP_SECTOR_SIZE 64
124 #define STM32F7_OTP_SIZE 1024
125 #define STM32F7_OTP_BANK_BASE 0x1ff0f000
126 #define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
127
128 #define STM32_FLASH_BASE 0x40023c00
129 #define STM32_FLASH_ACR 0x40023c00
130 #define STM32_FLASH_KEYR 0x40023c04
131 #define STM32_FLASH_OPTKEYR 0x40023c08
132 #define STM32_FLASH_SR 0x40023c0C
133 #define STM32_FLASH_CR 0x40023c10
134 #define STM32_FLASH_OPTCR 0x40023c14
135 #define STM32_FLASH_OPTCR1 0x40023c18
136 #define STM32_FLASH_OPTCR2 0x40023c1c
137
138 /* FLASH_CR register bits */
139 #define FLASH_PG (1 << 0)
140 #define FLASH_SER (1 << 1)
141 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
142 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
143 #define FLASH_STRT (1 << 16)
144 #define FLASH_PSIZE_8 (0 << 8)
145 #define FLASH_PSIZE_16 (1 << 8)
146 #define FLASH_PSIZE_32 (2 << 8)
147 #define FLASH_PSIZE_64 (3 << 8)
148 /* The sector number encoding is not straight binary for dual bank flash. */
149 #define FLASH_SNB(a) ((a) << 3)
150 #define FLASH_LOCK (1 << 31)
151
152 /* FLASH_SR register bits */
153 #define FLASH_BSY (1 << 16)
154 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
155 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
156 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
157 #define FLASH_WRPERR (1 << 4) /* Write protection error */
158 #define FLASH_OPERR (1 << 1) /* Operation error */
159
160 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
161
162 /* STM32_FLASH_OPTCR register bits */
163 #define OPTCR_LOCK (1 << 0)
164 #define OPTCR_START (1 << 1)
165 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
166 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
167 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
168
169 /* STM32_FLASH_OPTCR2 register bits */
170 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
171
172 /* register unlock keys */
173 #define KEY1 0x45670123
174 #define KEY2 0xCDEF89AB
175
176 /* option register unlock key */
177 #define OPTKEY1 0x08192A3B
178 #define OPTKEY2 0x4C5D6E7F
179
180 struct stm32x_options {
181 uint8_t RDP;
182 uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
183 uint32_t protection;
184 uint32_t boot_addr;
185 uint32_t optcr2_pcrop;
186 };
187
188 struct stm32x_flash_bank {
189 struct stm32x_options option_bytes;
190 bool probed;
191 bool otp_unlocked;
192 bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
193 bool has_extra_options; /* F42x/43x/469/479/7xx */
194 bool has_boot_addr; /* F7xx */
195 bool has_optcr2_pcrop; /* F72x/73x */
196 unsigned int protection_bits; /* F413/423 */
197 uint32_t user_bank_size;
198 };
199
200 static bool stm32x_is_otp(struct flash_bank *bank)
201 {
202 return bank->base == STM32F2_OTP_BANK_BASE ||
203 bank->base == STM32F7_OTP_BANK_BASE;
204 }
205
206 static bool stm32x_otp_is_f7(struct flash_bank *bank)
207 {
208 return bank->base == STM32F7_OTP_BANK_BASE;
209 }
210
211 static int stm32x_is_otp_unlocked(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 return stm32x_info->otp_unlocked;
216 }
217
218 static int stm32x_otp_disable(struct flash_bank *bank)
219 {
220 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
221
222 LOG_INFO("OTP memory bank #%u is disabled for write commands.",
223 bank->bank_number);
224 stm32x_info->otp_unlocked = false;
225 return ERROR_OK;
226 }
227
228 static int stm32x_otp_enable(struct flash_bank *bank)
229 {
230 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
231
232 if (!stm32x_info->otp_unlocked) {
233 LOG_INFO("OTP memory bank #%u is enabled for write commands.",
234 bank->bank_number);
235 stm32x_info->otp_unlocked = true;
236 } else {
237 LOG_WARNING("OTP memory bank #%u is already enabled for write commands.",
238 bank->bank_number);
239 }
240 return ERROR_OK;
241 }
242
243 /* flash bank stm32x <base> <size> 0 0 <target#>
244 */
245 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
246 {
247 struct stm32x_flash_bank *stm32x_info;
248
249 if (CMD_ARGC < 6)
250 return ERROR_COMMAND_SYNTAX_ERROR;
251
252 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
253 bank->driver_priv = stm32x_info;
254
255 stm32x_info->probed = false;
256 stm32x_info->otp_unlocked = false;
257 stm32x_info->user_bank_size = bank->size;
258
259 return ERROR_OK;
260 }
261
262 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
263 {
264 return reg;
265 }
266
267 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
268 {
269 struct target *target = bank->target;
270 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
271 }
272
273 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
274 {
275 struct target *target = bank->target;
276 uint32_t status;
277 int retval = ERROR_OK;
278
279 /* wait for busy to clear */
280 for (;;) {
281 retval = stm32x_get_flash_status(bank, &status);
282 if (retval != ERROR_OK)
283 return retval;
284 LOG_DEBUG("status: 0x%" PRIx32, status);
285 if ((status & FLASH_BSY) == 0)
286 break;
287 if (timeout-- <= 0) {
288 LOG_ERROR("timed out waiting for flash");
289 return ERROR_FAIL;
290 }
291 alive_sleep(1);
292 }
293
294
295 if (status & FLASH_WRPERR) {
296 LOG_ERROR("stm32x device protected");
297 retval = ERROR_FAIL;
298 }
299
300 /* Clear but report errors */
301 if (status & FLASH_ERROR) {
302 if (retval == ERROR_OK)
303 retval = ERROR_FAIL;
304 /* If this operation fails, we ignore it and report the original
305 * retval
306 */
307 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
308 status & FLASH_ERROR);
309 }
310 return retval;
311 }
312
313 static int stm32x_unlock_reg(struct target *target)
314 {
315 uint32_t ctrl;
316
317 /* first check if not already unlocked
318 * otherwise writing on STM32_FLASH_KEYR will fail
319 */
320 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
321 if (retval != ERROR_OK)
322 return retval;
323
324 if ((ctrl & FLASH_LOCK) == 0)
325 return ERROR_OK;
326
327 /* unlock flash registers */
328 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
329 if (retval != ERROR_OK)
330 return retval;
331
332 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
333 if (retval != ERROR_OK)
334 return retval;
335
336 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
337 if (retval != ERROR_OK)
338 return retval;
339
340 if (ctrl & FLASH_LOCK) {
341 LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32, ctrl);
342 return ERROR_TARGET_FAILURE;
343 }
344
345 return ERROR_OK;
346 }
347
348 static int stm32x_unlock_option_reg(struct target *target)
349 {
350 uint32_t ctrl;
351
352 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
353 if (retval != ERROR_OK)
354 return retval;
355
356 if ((ctrl & OPTCR_LOCK) == 0)
357 return ERROR_OK;
358
359 /* unlock option registers */
360 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
361 if (retval != ERROR_OK)
362 return retval;
363
364 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
365 if (retval != ERROR_OK)
366 return retval;
367
368 retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
369 if (retval != ERROR_OK)
370 return retval;
371
372 if (ctrl & OPTCR_LOCK) {
373 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
374 return ERROR_TARGET_FAILURE;
375 }
376
377 return ERROR_OK;
378 }
379
380 static int stm32x_read_options(struct flash_bank *bank)
381 {
382 uint32_t optiondata;
383 struct stm32x_flash_bank *stm32x_info = NULL;
384 struct target *target = bank->target;
385
386 stm32x_info = bank->driver_priv;
387
388 /* read current option bytes */
389 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
390 if (retval != ERROR_OK)
391 return retval;
392
393 /* caution: F2 implements 5 bits (WDG_SW only)
394 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
395 stm32x_info->option_bytes.user_options = optiondata & 0xfc;
396 stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
397 stm32x_info->option_bytes.protection =
398 (optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
399
400 if (stm32x_info->has_extra_options) {
401 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
402 stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
403 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
404 }
405
406 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
407 retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
408 if (retval != ERROR_OK)
409 return retval;
410
411 /* FLASH_OPTCR1 has quite different meanings ... */
412 if (stm32x_info->has_boot_addr) {
413 /* for F7xx it contains boot0 and boot1 */
414 stm32x_info->option_bytes.boot_addr = optiondata;
415 } else {
416 /* for F42x/43x/469/479 it contains 12 additional protection bits */
417 stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
418 }
419 }
420
421 if (stm32x_info->has_optcr2_pcrop) {
422 retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
423 if (retval != ERROR_OK)
424 return retval;
425
426 stm32x_info->option_bytes.optcr2_pcrop = optiondata;
427 if (stm32x_info->has_optcr2_pcrop &&
428 (stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
429 LOG_INFO("PCROP Engaged");
430 }
431 } else {
432 stm32x_info->option_bytes.optcr2_pcrop = 0x0;
433 }
434
435 if (stm32x_info->option_bytes.RDP != 0xAA)
436 LOG_INFO("Device Security Bit Set");
437
438 return ERROR_OK;
439 }
440
441 static int stm32x_write_options(struct flash_bank *bank)
442 {
443 struct stm32x_flash_bank *stm32x_info = NULL;
444 struct target *target = bank->target;
445 uint32_t optiondata, optiondata2;
446
447 stm32x_info = bank->driver_priv;
448
449 int retval = stm32x_unlock_option_reg(target);
450 if (retval != ERROR_OK)
451 return retval;
452
453 /* rebuild option data */
454 optiondata = stm32x_info->option_bytes.user_options & 0xfc;
455 optiondata |= stm32x_info->option_bytes.RDP << 8;
456 optiondata |= (stm32x_info->option_bytes.protection &
457 (~(0xffff << stm32x_info->protection_bits))) << 16;
458
459 if (stm32x_info->has_extra_options) {
460 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
461 optiondata |= (stm32x_info->option_bytes.user_options &
462 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
463 }
464
465 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
466 if (stm32x_info->has_boot_addr) {
467 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
468 optiondata2 = stm32x_info->option_bytes.boot_addr;
469 } else {
470 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
471 optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
472 }
473
474 retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
475 if (retval != ERROR_OK)
476 return retval;
477 }
478
479 /* program extra pcrop register */
480 if (stm32x_info->has_optcr2_pcrop) {
481 retval = target_write_u32(target, STM32_FLASH_OPTCR2,
482 stm32x_info->option_bytes.optcr2_pcrop);
483 if (retval != ERROR_OK)
484 return retval;
485 }
486
487 /* program options */
488 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
489 if (retval != ERROR_OK)
490 return retval;
491
492 /* start programming cycle */
493 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
494 if (retval != ERROR_OK)
495 return retval;
496
497 /* wait for completion, this might trigger a security erase and take a while */
498 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
499 if (retval != ERROR_OK)
500 return retval;
501
502 /* relock registers */
503 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
504 if (retval != ERROR_OK)
505 return retval;
506
507 return ERROR_OK;
508 }
509
510 static int stm32x_otp_read_protect(struct flash_bank *bank)
511 {
512 struct target *target = bank->target;
513 uint32_t lock_base;
514 int retval;
515 uint8_t lock;
516
517 lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
518 : STM32F2_OTP_LOCK_BASE;
519
520 for (unsigned int i = 0; i < bank->num_sectors; i++) {
521 retval = target_read_u8(target, lock_base + i, &lock);
522 if (retval != ERROR_OK)
523 return retval;
524 bank->sectors[i].is_protected = !lock;
525 }
526
527 return ERROR_OK;
528 }
529
530 static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first,
531 unsigned int last)
532 {
533 struct target *target = bank->target;
534 uint32_t lock_base;
535 int i, retval;
536 uint8_t lock;
537
538 assert((first <= last) && (last < bank->num_sectors));
539
540 lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
541 : STM32F2_OTP_LOCK_BASE;
542
543 for (i = first; first <= last; i++) {
544 retval = target_read_u8(target, lock_base + i, &lock);
545 if (retval != ERROR_OK)
546 return retval;
547 if (lock)
548 continue;
549
550 lock = 0xff;
551 retval = target_write_u8(target, lock_base + i, lock);
552 if (retval != ERROR_OK)
553 return retval;
554 }
555
556 return ERROR_OK;
557 }
558
559 static int stm32x_protect_check(struct flash_bank *bank)
560 {
561 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
562 struct flash_sector *prot_blocks;
563 unsigned int num_prot_blocks;
564 int retval;
565
566 /* if it's the OTP bank, look at the lock bits there */
567 if (stm32x_is_otp(bank))
568 return stm32x_otp_read_protect(bank);
569
570 /* read write protection settings */
571 retval = stm32x_read_options(bank);
572 if (retval != ERROR_OK) {
573 LOG_DEBUG("unable to read option bytes");
574 return retval;
575 }
576
577 if (bank->prot_blocks) {
578 num_prot_blocks = bank->num_prot_blocks;
579 prot_blocks = bank->prot_blocks;
580 } else {
581 num_prot_blocks = bank->num_sectors;
582 prot_blocks = bank->sectors;
583 }
584
585 for (unsigned int i = 0; i < num_prot_blocks; i++)
586 prot_blocks[i].is_protected =
587 ~(stm32x_info->option_bytes.protection >> i) & 1;
588
589 return ERROR_OK;
590 }
591
592 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
593 unsigned int last)
594 {
595 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
596 struct target *target = bank->target;
597
598 if (stm32x_is_otp(bank)) {
599 LOG_ERROR("Cannot erase OTP memory");
600 return ERROR_FAIL;
601 }
602
603 assert((first <= last) && (last < bank->num_sectors));
604
605 if (bank->target->state != TARGET_HALTED) {
606 LOG_ERROR("Target not halted");
607 return ERROR_TARGET_NOT_HALTED;
608 }
609
610 int retval;
611 retval = stm32x_unlock_reg(target);
612 if (retval != ERROR_OK)
613 return retval;
614
615 /*
616 Sector Erase
617 To erase a sector, follow the procedure below:
618 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
619 FLASH_SR register
620 2. Set the SER bit and select the sector
621 you wish to erase (SNB) in the FLASH_CR register
622 3. Set the STRT bit in the FLASH_CR register
623 4. Wait for the BSY bit to be cleared
624 */
625
626 for (unsigned int i = first; i <= last; i++) {
627 unsigned int snb;
628 if (stm32x_info->has_large_mem && i >= (bank->num_sectors / 2))
629 snb = (i - (bank->num_sectors / 2)) | 0x10;
630 else
631 snb = i;
632
633 retval = target_write_u32(target,
634 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT);
635 if (retval != ERROR_OK)
636 return retval;
637
638 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
639 if (retval != ERROR_OK)
640 return retval;
641 }
642
643 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
644 if (retval != ERROR_OK)
645 return retval;
646
647 return ERROR_OK;
648 }
649
650 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
651 unsigned int last)
652 {
653 struct target *target = bank->target;
654 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
655
656 if (target->state != TARGET_HALTED) {
657 LOG_ERROR("Target not halted");
658 return ERROR_TARGET_NOT_HALTED;
659 }
660
661 if (stm32x_is_otp(bank)) {
662 if (!set) {
663 LOG_ERROR("OTP protection can only be enabled");
664 return ERROR_COMMAND_ARGUMENT_INVALID;
665 }
666
667 return stm32x_otp_protect(bank, first, last);
668 }
669
670 /* read protection settings */
671 int retval = stm32x_read_options(bank);
672 if (retval != ERROR_OK) {
673 LOG_DEBUG("unable to read option bytes");
674 return retval;
675 }
676
677 for (unsigned int i = first; i <= last; i++) {
678 if (set)
679 stm32x_info->option_bytes.protection &= ~(1 << i);
680 else
681 stm32x_info->option_bytes.protection |= (1 << i);
682 }
683
684 retval = stm32x_write_options(bank);
685 if (retval != ERROR_OK)
686 return retval;
687
688 return ERROR_OK;
689 }
690
691 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
692 uint32_t offset, uint32_t count)
693 {
694 struct target *target = bank->target;
695 uint32_t buffer_size = 16384;
696 struct working_area *write_algorithm;
697 struct working_area *source;
698 uint32_t address = bank->base + offset;
699 struct reg_param reg_params[5];
700 struct armv7m_algorithm armv7m_info;
701 int retval = ERROR_OK;
702
703 static const uint8_t stm32x_flash_write_code[] = {
704 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
705 };
706
707 if (stm32x_is_otp(bank) && !stm32x_is_otp_unlocked(bank)) {
708 LOG_ERROR("OTP memory bank is disabled for write commands.");
709 return ERROR_FAIL;
710 }
711
712 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
713 &write_algorithm) != ERROR_OK) {
714 LOG_WARNING("no working area available, can't do block memory writes");
715 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
716 }
717
718 retval = target_write_buffer(target, write_algorithm->address,
719 sizeof(stm32x_flash_write_code),
720 stm32x_flash_write_code);
721 if (retval != ERROR_OK) {
722 target_free_working_area(target, write_algorithm);
723 return retval;
724 }
725
726 /* memory buffer */
727 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
728 buffer_size /= 2;
729 if (buffer_size <= 256) {
730 /* we already allocated the writing code, but failed to get a
731 * buffer, free the algorithm */
732 target_free_working_area(target, write_algorithm);
733
734 LOG_WARNING("no large enough working area available, can't do block memory writes");
735 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
736 }
737 }
738
739 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
740 armv7m_info.core_mode = ARM_MODE_THREAD;
741
742 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
743 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
744 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
745 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
746 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
747
748 buf_set_u32(reg_params[0].value, 0, 32, source->address);
749 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
750 buf_set_u32(reg_params[2].value, 0, 32, address);
751 buf_set_u32(reg_params[3].value, 0, 32, count);
752 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
753
754 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
755 0, NULL,
756 5, reg_params,
757 source->address, source->size,
758 write_algorithm->address, 0,
759 &armv7m_info);
760
761 if (retval == ERROR_FLASH_OPERATION_FAILED) {
762 LOG_ERROR("error executing stm32x flash write algorithm");
763
764 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
765
766 if (error & FLASH_WRPERR)
767 LOG_ERROR("flash memory write protected");
768
769 if (error != 0) {
770 LOG_ERROR("flash write failed = 0x%08" PRIx32, error);
771 /* Clear but report errors */
772 target_write_u32(target, STM32_FLASH_SR, error);
773 retval = ERROR_FAIL;
774 }
775 }
776
777 target_free_working_area(target, source);
778 target_free_working_area(target, write_algorithm);
779
780 destroy_reg_param(&reg_params[0]);
781 destroy_reg_param(&reg_params[1]);
782 destroy_reg_param(&reg_params[2]);
783 destroy_reg_param(&reg_params[3]);
784 destroy_reg_param(&reg_params[4]);
785
786 return retval;
787 }
788
789 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
790 uint32_t offset, uint32_t count)
791 {
792 struct target *target = bank->target;
793 uint32_t words_remaining = (count / 2);
794 uint32_t bytes_remaining = (count & 0x00000001);
795 uint32_t address = bank->base + offset;
796 uint32_t bytes_written = 0;
797 int retval;
798
799 if (bank->target->state != TARGET_HALTED) {
800 LOG_ERROR("Target not halted");
801 return ERROR_TARGET_NOT_HALTED;
802 }
803
804 if (offset & 0x1) {
805 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
806 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
807 }
808
809 retval = stm32x_unlock_reg(target);
810 if (retval != ERROR_OK)
811 return retval;
812
813 /* multiple half words (2-byte) to be programmed? */
814 if (words_remaining > 0) {
815 /* try using a block write */
816 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
817 if (retval != ERROR_OK) {
818 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
819 /* if block write failed (no sufficient working area),
820 * we use normal (slow) single dword accesses */
821 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
822 }
823 } else {
824 buffer += words_remaining * 2;
825 address += words_remaining * 2;
826 words_remaining = 0;
827 }
828 }
829
830 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
831 return retval;
832
833 /*
834 Standard programming
835 The Flash memory programming sequence is as follows:
836 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
837 FLASH_SR register.
838 2. Set the PG bit in the FLASH_CR register
839 3. Perform the data write operation(s) to the desired memory address (inside main
840 memory block or OTP area):
841 – – Half-word access in case of x16 parallelism
842 – Word access in case of x32 parallelism
843 –
844 4.
845 Byte access in case of x8 parallelism
846 Double word access in case of x64 parallelism
847 Wait for the BSY bit to be cleared
848 */
849 while (words_remaining > 0) {
850 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
851 FLASH_PG | FLASH_PSIZE_16);
852 if (retval != ERROR_OK)
853 return retval;
854
855 retval = target_write_memory(target, address, 2, 1, buffer + bytes_written);
856 if (retval != ERROR_OK)
857 return retval;
858
859 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
860 if (retval != ERROR_OK)
861 return retval;
862
863 bytes_written += 2;
864 words_remaining--;
865 address += 2;
866 }
867
868 if (bytes_remaining) {
869 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
870 FLASH_PG | FLASH_PSIZE_8);
871 if (retval != ERROR_OK)
872 return retval;
873 retval = target_write_u8(target, address, buffer[bytes_written]);
874 if (retval != ERROR_OK)
875 return retval;
876
877 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
878 if (retval != ERROR_OK)
879 return retval;
880 }
881
882 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
883 }
884
885 static void setup_sector(struct flash_bank *bank, unsigned int i,
886 unsigned int size)
887 {
888 assert(i < bank->num_sectors);
889 bank->sectors[i].offset = bank->size;
890 bank->sectors[i].size = size;
891 bank->size += bank->sectors[i].size;
892 LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
893 }
894
895 static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb)
896 {
897 if (i < 4)
898 return max_sector_size_in_kb / 8;
899 if (i == 4)
900 return max_sector_size_in_kb / 2;
901 return max_sector_size_in_kb;
902 }
903
904 static unsigned int calculate_number_of_sectors(struct flash_bank *bank,
905 uint16_t flash_size_in_kb,
906 uint16_t max_sector_size_in_kb)
907 {
908 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
909 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
910 unsigned int nr_sectors;
911
912 /* Dual Bank Flash has two identically-arranged banks of sectors. */
913 if (stm32x_info->has_large_mem)
914 remaining_flash_size_in_kb /= 2;
915
916 for (nr_sectors = 0; remaining_flash_size_in_kb > 0; nr_sectors++) {
917 uint16_t size_in_kb = sector_size_in_kb(nr_sectors, max_sector_size_in_kb);
918 if (size_in_kb > remaining_flash_size_in_kb) {
919 LOG_INFO("%s Bank %" PRIu16 " kiB final sector clipped to %" PRIu16 " kiB",
920 stm32x_info->has_large_mem ? "Dual" : "Single",
921 flash_size_in_kb, remaining_flash_size_in_kb);
922 remaining_flash_size_in_kb = 0;
923 } else {
924 remaining_flash_size_in_kb -= size_in_kb;
925 }
926 }
927
928 return stm32x_info->has_large_mem ? nr_sectors*2 : nr_sectors;
929 }
930
931 static void setup_bank(struct flash_bank *bank, unsigned int start,
932 uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
933 {
934 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
935 unsigned int sector_index = 0;
936 while (remaining_flash_size_in_kb > 0) {
937 uint16_t size_in_kb = sector_size_in_kb(sector_index, max_sector_size_in_kb);
938 if (size_in_kb > remaining_flash_size_in_kb) {
939 /* Clip last sector. Already warned in
940 * calculate_number_of_sectors. */
941 size_in_kb = remaining_flash_size_in_kb;
942 }
943 setup_sector(bank, start + sector_index, size_in_kb * 1024);
944 remaining_flash_size_in_kb -= size_in_kb;
945 sector_index++;
946 }
947 }
948
949 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
950 {
951 /* this checks for a stm32f4x errata issue where a
952 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
953 * If the issue is detected target is forced to stm32f4x Rev A.
954 * Only effects Rev A silicon */
955
956 struct target *target = bank->target;
957
958 /* read stm32 device id register */
959 int retval = target_read_u32(target, 0xE0042000, device_id);
960 if (retval != ERROR_OK)
961 return retval;
962
963 if ((*device_id & 0xfff) == 0x411
964 && cortex_m_get_impl_part(target) == CORTEX_M4_PARTNO) {
965 *device_id &= ~((0xFFFF << 16) | 0xfff);
966 *device_id |= (0x1000 << 16) | 0x413;
967 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
968 }
969 return retval;
970 }
971
972 static int stm32x_probe(struct flash_bank *bank)
973 {
974 struct target *target = bank->target;
975 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
976 unsigned int num_prot_blocks, num_sectors;
977 uint16_t flash_size_in_kb;
978 uint16_t otp_size_in_b;
979 uint16_t otp_sector_size;
980 uint32_t flash_size_reg = 0x1FFF7A22;
981 uint16_t max_sector_size_in_kb = 128;
982 uint16_t max_flash_size_in_kb;
983 uint32_t device_id;
984 uint32_t base_address = 0x08000000;
985
986 stm32x_info->probed = false;
987 stm32x_info->has_large_mem = false;
988 stm32x_info->has_boot_addr = false;
989 stm32x_info->has_extra_options = false;
990 stm32x_info->has_optcr2_pcrop = false;
991 stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
992 num_prot_blocks = 0;
993
994 free(bank->sectors);
995 bank->num_sectors = 0;
996 bank->sectors = NULL;
997
998 free(bank->prot_blocks);
999 bank->num_prot_blocks = 0;
1000 bank->prot_blocks = NULL;
1001
1002 if (!target_was_examined(target)) {
1003 LOG_ERROR("Target not examined yet");
1004 return ERROR_TARGET_NOT_EXAMINED;
1005 }
1006
1007 /* if explicitly called out as OTP bank, short circuit probe */
1008 if (stm32x_is_otp(bank)) {
1009 if (stm32x_otp_is_f7(bank)) {
1010 otp_size_in_b = STM32F7_OTP_SIZE;
1011 otp_sector_size = STM32F7_OTP_SECTOR_SIZE;
1012 } else {
1013 otp_size_in_b = STM32F2_OTP_SIZE;
1014 otp_sector_size = STM32F2_OTP_SECTOR_SIZE;
1015 }
1016
1017 num_sectors = otp_size_in_b / otp_sector_size;
1018 LOG_INFO("flash size = %" PRIu16 " bytes", otp_size_in_b);
1019
1020 assert(num_sectors > 0);
1021
1022 bank->num_sectors = num_sectors;
1023 bank->sectors = calloc(sizeof(struct flash_sector), num_sectors);
1024
1025 if (stm32x_otp_is_f7(bank))
1026 bank->size = STM32F7_OTP_SIZE;
1027 else
1028 bank->size = STM32F2_OTP_SIZE;
1029
1030 for (unsigned int i = 0; i < num_sectors; i++) {
1031 bank->sectors[i].offset = i * otp_sector_size;
1032 bank->sectors[i].size = otp_sector_size;
1033 bank->sectors[i].is_erased = 1;
1034 bank->sectors[i].is_protected = 0;
1035 }
1036
1037 stm32x_info->probed = true;
1038 return ERROR_OK;
1039 }
1040
1041 /* read stm32 device id register */
1042 int retval = stm32x_get_device_id(bank, &device_id);
1043 if (retval != ERROR_OK)
1044 return retval;
1045 LOG_INFO("device id = 0x%08" PRIx32, device_id);
1046 device_id &= 0xfff; /* only bits 0-11 are used further on */
1047
1048 /* set max flash size depending on family, id taken from AN2606 */
1049 switch (device_id) {
1050 case 0x411: /* F20x/21x */
1051 case 0x413: /* F40x/41x */
1052 max_flash_size_in_kb = 1024;
1053 break;
1054
1055 case 0x419: /* F42x/43x */
1056 case 0x434: /* F469/479 */
1057 stm32x_info->has_extra_options = true;
1058 max_flash_size_in_kb = 2048;
1059 break;
1060
1061 case 0x423: /* F401xB/C */
1062 max_flash_size_in_kb = 256;
1063 break;
1064
1065 case 0x421: /* F446 */
1066 case 0x431: /* F411 */
1067 case 0x433: /* F401xD/E */
1068 case 0x441: /* F412 */
1069 max_flash_size_in_kb = 512;
1070 break;
1071
1072 case 0x458: /* F410 */
1073 max_flash_size_in_kb = 128;
1074 break;
1075
1076 case 0x449: /* F74x/75x */
1077 max_flash_size_in_kb = 1024;
1078 max_sector_size_in_kb = 256;
1079 flash_size_reg = 0x1FF0F442;
1080 stm32x_info->has_extra_options = true;
1081 stm32x_info->has_boot_addr = true;
1082 break;
1083
1084 case 0x451: /* F76x/77x */
1085 max_flash_size_in_kb = 2048;
1086 max_sector_size_in_kb = 256;
1087 flash_size_reg = 0x1FF0F442;
1088 stm32x_info->has_extra_options = true;
1089 stm32x_info->has_boot_addr = true;
1090 break;
1091
1092 case 0x452: /* F72x/73x */
1093 max_flash_size_in_kb = 512;
1094 flash_size_reg = 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
1095 stm32x_info->has_extra_options = true;
1096 stm32x_info->has_boot_addr = true;
1097 stm32x_info->has_optcr2_pcrop = true;
1098 break;
1099
1100 case 0x463: /* F413x/423x */
1101 max_flash_size_in_kb = 1536;
1102 stm32x_info->has_extra_options = true;
1103 stm32x_info->protection_bits = 15;
1104 num_prot_blocks = 15;
1105 break;
1106
1107 default:
1108 LOG_WARNING("Cannot identify target as a STM32 family.");
1109 return ERROR_FAIL;
1110 }
1111
1112 /* get flash size from target. */
1113 retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
1114
1115 /* failed reading flash size or flash size invalid (early silicon),
1116 * default to max target family */
1117 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
1118 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16 "k flash",
1119 max_flash_size_in_kb);
1120 flash_size_in_kb = max_flash_size_in_kb;
1121 }
1122
1123 /* if the user sets the size manually then ignore the probed value
1124 * this allows us to work around devices that have a invalid flash size register value */
1125 if (stm32x_info->user_bank_size) {
1126 LOG_INFO("ignoring flash probed value, using configured bank size");
1127 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1128 }
1129
1130 LOG_INFO("flash size = %" PRIu16 " KiB", flash_size_in_kb);
1131
1132 /* did we assign flash size? */
1133 assert(flash_size_in_kb != 0xffff);
1134
1135 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
1136 if ((device_id == 0x419) || (device_id == 0x434)) {
1137 uint32_t optiondata;
1138 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
1139 if (retval != ERROR_OK) {
1140 LOG_DEBUG("unable to read option bytes");
1141 return retval;
1142 }
1143 if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
1144 stm32x_info->has_large_mem = true;
1145 LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1146 } else {
1147 stm32x_info->has_large_mem = false;
1148 LOG_INFO("Single Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1149 }
1150 }
1151
1152 /* F76x/77x devices have a dual bank option */
1153 if (device_id == 0x451) {
1154 uint32_t optiondata;
1155 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
1156 if (retval != ERROR_OK) {
1157 LOG_DEBUG("unable to read option bytes");
1158 return retval;
1159 }
1160 if (optiondata & OPTCR_NDBANK) {
1161 stm32x_info->has_large_mem = false;
1162 LOG_INFO("Single Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
1163 } else {
1164 stm32x_info->has_large_mem = true;
1165 max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
1166 LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
1167 }
1168 }
1169
1170 /* calculate numbers of pages */
1171 unsigned int num_pages = calculate_number_of_sectors(
1172 bank, flash_size_in_kb, max_sector_size_in_kb);
1173
1174 bank->base = base_address;
1175 bank->num_sectors = num_pages;
1176 bank->sectors = calloc(num_pages, sizeof(struct flash_sector));
1177 for (unsigned int i = 0; i < num_pages; i++) {
1178 bank->sectors[i].is_erased = -1;
1179 bank->sectors[i].is_protected = 0;
1180 }
1181 bank->size = 0;
1182 LOG_DEBUG("allocated %u sectors", num_pages);
1183
1184 /* F76x/77x in dual bank mode */
1185 if ((device_id == 0x451) && stm32x_info->has_large_mem)
1186 num_prot_blocks = num_pages >> 1;
1187
1188 if (num_prot_blocks) {
1189 bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
1190 for (unsigned int i = 0; i < num_prot_blocks; i++)
1191 bank->prot_blocks[i].is_protected = 0;
1192 LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
1193 }
1194
1195 if (stm32x_info->has_large_mem) {
1196 /* dual-bank */
1197 setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
1198 setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
1199 max_sector_size_in_kb);
1200
1201 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1202 if (device_id == 0x451) {
1203 for (unsigned int i = 0; i < num_prot_blocks; i++) {
1204 bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
1205 bank->prot_blocks[i].size = bank->sectors[i << 1].size
1206 + bank->sectors[(i << 1) + 1].size;
1207 }
1208 }
1209 } else {
1210 /* single-bank */
1211 setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
1212
1213 /* F413/F423, sectors 14 and 15 share one common protection bit */
1214 if (device_id == 0x463) {
1215 for (unsigned int i = 0; i < num_prot_blocks; i++) {
1216 bank->prot_blocks[i].offset = bank->sectors[i].offset;
1217 bank->prot_blocks[i].size = bank->sectors[i].size;
1218 }
1219 bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
1220 }
1221 }
1222 bank->num_prot_blocks = num_prot_blocks;
1223 assert((bank->size >> 10) == flash_size_in_kb);
1224
1225 stm32x_info->probed = true;
1226 return ERROR_OK;
1227 }
1228
1229 static int stm32x_auto_probe(struct flash_bank *bank)
1230 {
1231 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1232 if (stm32x_info->probed)
1233 return ERROR_OK;
1234 return stm32x_probe(bank);
1235 }
1236
1237 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1238 {
1239 uint32_t dbgmcu_idcode;
1240
1241 /* read stm32 device id register */
1242 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1243 if (retval != ERROR_OK)
1244 return retval;
1245
1246 uint16_t device_id = dbgmcu_idcode & 0xfff;
1247 uint16_t rev_id = dbgmcu_idcode >> 16;
1248 const char *device_str;
1249 const char *rev_str = NULL;
1250
1251 switch (device_id) {
1252 case 0x411:
1253 device_str = "STM32F2xx";
1254
1255 switch (rev_id) {
1256 case 0x1000:
1257 rev_str = "A";
1258 break;
1259
1260 case 0x2000:
1261 rev_str = "B";
1262 break;
1263
1264 case 0x1001:
1265 rev_str = "Z";
1266 break;
1267
1268 case 0x2001:
1269 rev_str = "Y";
1270 break;
1271
1272 case 0x2003:
1273 rev_str = "X";
1274 break;
1275
1276 case 0x2007:
1277 rev_str = "1";
1278 break;
1279
1280 case 0x200F:
1281 rev_str = "V";
1282 break;
1283
1284 case 0x201F:
1285 rev_str = "2";
1286 break;
1287 }
1288 break;
1289
1290 case 0x413:
1291 case 0x419:
1292 case 0x434:
1293 device_str = "STM32F4xx";
1294
1295 switch (rev_id) {
1296 case 0x1000:
1297 rev_str = "A";
1298 break;
1299
1300 case 0x1001:
1301 rev_str = "Z";
1302 break;
1303
1304 case 0x1003:
1305 rev_str = "Y";
1306 break;
1307
1308 case 0x1007:
1309 rev_str = "1";
1310 break;
1311
1312 case 0x2001:
1313 rev_str = "3";
1314 break;
1315 }
1316 break;
1317
1318 case 0x421:
1319 device_str = "STM32F446";
1320
1321 switch (rev_id) {
1322 case 0x1000:
1323 rev_str = "A";
1324 break;
1325 }
1326 break;
1327
1328 case 0x423:
1329 case 0x431:
1330 case 0x433:
1331 case 0x458:
1332 case 0x441:
1333 device_str = "STM32F4xx (Low Power)";
1334
1335 switch (rev_id) {
1336 case 0x1000:
1337 rev_str = "A";
1338 break;
1339
1340 case 0x1001:
1341 rev_str = "Z";
1342 break;
1343
1344 case 0x2000:
1345 rev_str = "B";
1346 break;
1347
1348 case 0x3000:
1349 rev_str = "C";
1350 break;
1351 }
1352 break;
1353
1354 case 0x449:
1355 device_str = "STM32F7[4|5]x";
1356
1357 switch (rev_id) {
1358 case 0x1000:
1359 rev_str = "A";
1360 break;
1361
1362 case 0x1001:
1363 rev_str = "Z";
1364 break;
1365 }
1366 break;
1367
1368 case 0x451:
1369 device_str = "STM32F7[6|7]x";
1370
1371 switch (rev_id) {
1372 case 0x1000:
1373 rev_str = "A";
1374 break;
1375 case 0x1001:
1376 rev_str = "Z";
1377 break;
1378 }
1379 break;
1380
1381 case 0x452:
1382 device_str = "STM32F7[2|3]x";
1383
1384 switch (rev_id) {
1385 case 0x1000:
1386 rev_str = "A";
1387 break;
1388 }
1389 break;
1390
1391 case 0x463:
1392 device_str = "STM32F4[1|2]3";
1393
1394 switch (rev_id) {
1395 case 0x1000:
1396 rev_str = "A";
1397 break;
1398 }
1399 break;
1400
1401 default:
1402 command_print_sameline(cmd, "Cannot identify target as a STM32F2/4/7\n");
1403 return ERROR_FAIL;
1404 }
1405
1406 if (rev_str)
1407 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1408 else
1409 command_print_sameline(cmd, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
1410
1411 return ERROR_OK;
1412 }
1413
1414 COMMAND_HANDLER(stm32x_handle_lock_command)
1415 {
1416 struct target *target = NULL;
1417 struct stm32x_flash_bank *stm32x_info = NULL;
1418
1419 if (CMD_ARGC < 1)
1420 return ERROR_COMMAND_SYNTAX_ERROR;
1421
1422 struct flash_bank *bank;
1423 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1424 if (retval != ERROR_OK)
1425 return retval;
1426
1427 stm32x_info = bank->driver_priv;
1428 target = bank->target;
1429
1430 if (target->state != TARGET_HALTED) {
1431 LOG_INFO("Target not halted");
1432 /* return ERROR_TARGET_NOT_HALTED; */
1433 }
1434
1435 if (stm32x_read_options(bank) != ERROR_OK) {
1436 command_print(CMD, "%s failed to read options", bank->driver->name);
1437 return ERROR_OK;
1438 }
1439
1440 /* set readout protection */
1441 stm32x_info->option_bytes.RDP = 0;
1442
1443 if (stm32x_write_options(bank) != ERROR_OK) {
1444 command_print(CMD, "%s failed to lock device", bank->driver->name);
1445 return ERROR_OK;
1446 }
1447
1448 command_print(CMD, "%s locked", bank->driver->name);
1449
1450 return ERROR_OK;
1451 }
1452
1453 COMMAND_HANDLER(stm32x_handle_unlock_command)
1454 {
1455 struct target *target = NULL;
1456 struct stm32x_flash_bank *stm32x_info = NULL;
1457
1458 if (CMD_ARGC < 1)
1459 return ERROR_COMMAND_SYNTAX_ERROR;
1460
1461 struct flash_bank *bank;
1462 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1463 if (retval != ERROR_OK)
1464 return retval;
1465
1466 stm32x_info = bank->driver_priv;
1467 target = bank->target;
1468
1469 if (target->state != TARGET_HALTED) {
1470 LOG_INFO("Target not halted");
1471 /* return ERROR_TARGET_NOT_HALTED; */
1472 }
1473
1474 if (stm32x_read_options(bank) != ERROR_OK) {
1475 command_print(CMD, "%s failed to read options", bank->driver->name);
1476 return ERROR_OK;
1477 }
1478
1479 /* clear readout protection and complementary option bytes
1480 * this will also force a device unlock if set */
1481 stm32x_info->option_bytes.RDP = 0xAA;
1482 if (stm32x_info->has_optcr2_pcrop) {
1483 stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1U << bank->num_sectors);
1484 }
1485
1486 if (stm32x_write_options(bank) != ERROR_OK) {
1487 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1488 return ERROR_OK;
1489 }
1490
1491 command_print(CMD, "%s unlocked.\n"
1492 "INFO: a reset or power cycle is required "
1493 "for the new settings to take effect.", bank->driver->name);
1494
1495 return ERROR_OK;
1496 }
1497
1498 static int stm32x_mass_erase(struct flash_bank *bank)
1499 {
1500 int retval;
1501 uint32_t flash_mer;
1502 struct target *target = bank->target;
1503 struct stm32x_flash_bank *stm32x_info = NULL;
1504
1505 if (target->state != TARGET_HALTED) {
1506 LOG_ERROR("Target not halted");
1507 return ERROR_TARGET_NOT_HALTED;
1508 }
1509
1510 stm32x_info = bank->driver_priv;
1511
1512 retval = stm32x_unlock_reg(target);
1513 if (retval != ERROR_OK)
1514 return retval;
1515
1516 /* mass erase flash memory */
1517 if (stm32x_info->has_large_mem)
1518 flash_mer = FLASH_MER | FLASH_MER1;
1519 else
1520 flash_mer = FLASH_MER;
1521
1522 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
1523 if (retval != ERROR_OK)
1524 return retval;
1525 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1526 flash_mer | FLASH_STRT);
1527 if (retval != ERROR_OK)
1528 return retval;
1529
1530 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
1531 if (retval != ERROR_OK)
1532 return retval;
1533
1534 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1535 if (retval != ERROR_OK)
1536 return retval;
1537
1538 return ERROR_OK;
1539 }
1540
1541 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1542 {
1543 if (CMD_ARGC != 1)
1544 return ERROR_COMMAND_SYNTAX_ERROR;
1545
1546 struct flash_bank *bank;
1547 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1548 if (retval != ERROR_OK)
1549 return retval;
1550
1551 retval = stm32x_mass_erase(bank);
1552 if (retval == ERROR_OK) {
1553 command_print(CMD, "stm32x mass erase complete");
1554 } else {
1555 command_print(CMD, "stm32x mass erase failed");
1556 }
1557
1558 return retval;
1559 }
1560
1561 COMMAND_HANDLER(stm32f2x_handle_options_read_command)
1562 {
1563 int retval;
1564 struct flash_bank *bank;
1565 struct stm32x_flash_bank *stm32x_info = NULL;
1566
1567 if (CMD_ARGC != 1)
1568 return ERROR_COMMAND_SYNTAX_ERROR;
1569
1570 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1571 if (retval != ERROR_OK)
1572 return retval;
1573
1574 retval = stm32x_read_options(bank);
1575 if (retval != ERROR_OK)
1576 return retval;
1577
1578 stm32x_info = bank->driver_priv;
1579 if (stm32x_info->has_extra_options) {
1580 if (stm32x_info->has_boot_addr) {
1581 uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
1582
1583 command_print(CMD, "stm32f2x user_options 0x%03" PRIX16 ","
1584 " boot_add0 0x%04" PRIX32 ", boot_add1 0x%04" PRIX32,
1585 stm32x_info->option_bytes.user_options,
1586 boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
1587 if (stm32x_info->has_optcr2_pcrop) {
1588 command_print(CMD, "stm32f2x optcr2_pcrop 0x%08" PRIX32,
1589 stm32x_info->option_bytes.optcr2_pcrop);
1590 }
1591 } else {
1592 command_print(CMD, "stm32f2x user_options 0x%03" PRIX16,
1593 stm32x_info->option_bytes.user_options);
1594 }
1595 } else {
1596 command_print(CMD, "stm32f2x user_options 0x%02" PRIX16,
1597 stm32x_info->option_bytes.user_options);
1598
1599 }
1600
1601 return retval;
1602 }
1603
1604 COMMAND_HANDLER(stm32f2x_handle_options_write_command)
1605 {
1606 int retval;
1607 struct flash_bank *bank;
1608 struct stm32x_flash_bank *stm32x_info = NULL;
1609 uint16_t user_options, boot_addr0, boot_addr1, options_mask;
1610
1611 if (CMD_ARGC < 1)
1612 return ERROR_COMMAND_SYNTAX_ERROR;
1613
1614 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1615 if (retval != ERROR_OK)
1616 return retval;
1617
1618 retval = stm32x_read_options(bank);
1619 if (retval != ERROR_OK)
1620 return retval;
1621
1622 stm32x_info = bank->driver_priv;
1623 if (stm32x_info->has_boot_addr) {
1624 if (CMD_ARGC != 4)
1625 return ERROR_COMMAND_SYNTAX_ERROR;
1626
1627 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
1628 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
1629 stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
1630 } else if (CMD_ARGC != 2) {
1631 return ERROR_COMMAND_SYNTAX_ERROR;
1632 }
1633
1634 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
1635 options_mask = !stm32x_info->has_extra_options ? ~0xfc :
1636 ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
1637 if (user_options & options_mask) {
1638 command_print(CMD, "stm32f2x invalid user_options");
1639 return ERROR_COMMAND_ARGUMENT_INVALID;
1640 }
1641
1642 stm32x_info->option_bytes.user_options = user_options;
1643
1644 if (stm32x_write_options(bank) != ERROR_OK) {
1645 command_print(CMD, "stm32f2x failed to write options");
1646 return ERROR_OK;
1647 }
1648
1649 /* switching between single- and dual-bank modes requires re-probe */
1650 /* ... and reprogramming of whole flash */
1651 stm32x_info->probed = false;
1652
1653 command_print(CMD, "stm32f2x write options complete.\n"
1654 "INFO: a reset or power cycle is required "
1655 "for the new settings to take effect.");
1656 return retval;
1657 }
1658
1659 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
1660 {
1661 int retval;
1662 struct flash_bank *bank;
1663 struct stm32x_flash_bank *stm32x_info = NULL;
1664 uint32_t optcr2_pcrop;
1665
1666 if (CMD_ARGC != 2)
1667 return ERROR_COMMAND_SYNTAX_ERROR;
1668
1669 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1670 if (retval != ERROR_OK)
1671 return retval;
1672
1673 stm32x_info = bank->driver_priv;
1674 if (!stm32x_info->has_optcr2_pcrop) {
1675 command_print(CMD, "no optcr2 register");
1676 return ERROR_COMMAND_ARGUMENT_INVALID;
1677 }
1678
1679 command_print(CMD, "INFO: To disable PCROP, set PCROP_RDP"
1680 " with PCROPi bits STILL SET, then\nlock device and"
1681 " finally unlock it. Clears PCROP and mass erases flash.");
1682
1683 retval = stm32x_read_options(bank);
1684 if (retval != ERROR_OK)
1685 return retval;
1686
1687 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
1688 stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
1689
1690 if (stm32x_write_options(bank) != ERROR_OK) {
1691 command_print(CMD, "stm32f2x failed to write options");
1692 return ERROR_OK;
1693 }
1694
1695 command_print(CMD, "stm32f2x optcr2_write complete.");
1696 return retval;
1697 }
1698
1699 COMMAND_HANDLER(stm32x_handle_otp_command)
1700 {
1701 if (CMD_ARGC != 2)
1702 return ERROR_COMMAND_SYNTAX_ERROR;
1703
1704 struct flash_bank *bank;
1705 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1706 if (retval != ERROR_OK)
1707 return retval;
1708 if (stm32x_is_otp(bank)) {
1709 if (strcmp(CMD_ARGV[1], "enable") == 0) {
1710 stm32x_otp_enable(bank);
1711 } else if (strcmp(CMD_ARGV[1], "disable") == 0) {
1712 stm32x_otp_disable(bank);
1713 } else if (strcmp(CMD_ARGV[1], "show") == 0) {
1714 command_print(CMD,
1715 "OTP memory bank #%u is %s for write commands.",
1716 bank->bank_number,
1717 stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
1718 } else {
1719 return ERROR_COMMAND_SYNTAX_ERROR;
1720 }
1721 } else {
1722 command_print(CMD, "Failed: not an OTP bank.");
1723 }
1724
1725 return retval;
1726 }
1727
1728 static const struct command_registration stm32f2x_exec_command_handlers[] = {
1729 {
1730 .name = "lock",
1731 .handler = stm32x_handle_lock_command,
1732 .mode = COMMAND_EXEC,
1733 .usage = "bank_id",
1734 .help = "Lock entire flash device.",
1735 },
1736 {
1737 .name = "unlock",
1738 .handler = stm32x_handle_unlock_command,
1739 .mode = COMMAND_EXEC,
1740 .usage = "bank_id",
1741 .help = "Unlock entire protected flash device.",
1742 },
1743 {
1744 .name = "mass_erase",
1745 .handler = stm32x_handle_mass_erase_command,
1746 .mode = COMMAND_EXEC,
1747 .usage = "bank_id",
1748 .help = "Erase entire flash device.",
1749 },
1750 {
1751 .name = "options_read",
1752 .handler = stm32f2x_handle_options_read_command,
1753 .mode = COMMAND_EXEC,
1754 .usage = "bank_id",
1755 .help = "Read and display device option bytes.",
1756 },
1757 {
1758 .name = "options_write",
1759 .handler = stm32f2x_handle_options_write_command,
1760 .mode = COMMAND_EXEC,
1761 .usage = "bank_id user_options [ boot_add0 boot_add1 ]",
1762 .help = "Write option bytes",
1763 },
1764 {
1765 .name = "optcr2_write",
1766 .handler = stm32f2x_handle_optcr2_write_command,
1767 .mode = COMMAND_EXEC,
1768 .usage = "bank_id optcr2",
1769 .help = "Write optcr2 word",
1770 },
1771 {
1772 .name = "otp",
1773 .handler = stm32x_handle_otp_command,
1774 .mode = COMMAND_EXEC,
1775 .usage = "bank_id (enable|disable|show)",
1776 .help = "OTP (One Time Programmable) memory write enable/disable.",
1777 },
1778 COMMAND_REGISTRATION_DONE
1779 };
1780
1781 static const struct command_registration stm32f2x_command_handlers[] = {
1782 {
1783 .name = "stm32f2x",
1784 .mode = COMMAND_ANY,
1785 .help = "stm32f2x flash command group",
1786 .usage = "",
1787 .chain = stm32f2x_exec_command_handlers,
1788 },
1789 COMMAND_REGISTRATION_DONE
1790 };
1791
1792 const struct flash_driver stm32f2x_flash = {
1793 .name = "stm32f2x",
1794 .commands = stm32f2x_command_handlers,
1795 .flash_bank_command = stm32x_flash_bank_command,
1796 .erase = stm32x_erase,
1797 .protect = stm32x_protect,
1798 .write = stm32x_write,
1799 .read = default_flash_read,
1800 .probe = stm32x_probe,
1801 .auto_probe = stm32x_auto_probe,
1802 .erase_check = default_flash_blank_check,
1803 .protect_check = stm32x_protect_check,
1804 .info = get_stm32x_info,
1805 .free_driver_priv = default_flash_free_driver_priv,
1806 };
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