1 /***************************************************************************
2 * Copyright (C) 2015 by Tobias Diedrich *
3 * <ranma+openwrt@tdiedrich.de> *
5 * based on the stmsmi code written by Antonio Borneo *
6 * <borneo.antonio@gmail.com> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc. *
22 ***************************************************************************/
24 * Driver for the Atheros AR7xxx/AR9xxx SPI flash interface.
26 * Since no SPI mode register is present, presumably only
27 * SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
29 * The SPI interface supports up to 3 chip selects, however the SPI flash
30 * used for booting the system must be connected to CS0.
32 * On boot, the first 4MiB of flash space are memory-mapped into the
33 * area bf000000 - bfffffff (4 copies), so the MIPS bootstrap
34 * vector bfc00000 is mapped to the beginning of the flash.
36 * By writing a 1 to the REMAP_DISABLE bit in the SPI_CONTROL register,
37 * the full area of 16MiB is mapped.
39 * By writing a 0 to the SPI_FUNCTION_SELECT register (write-only dword
40 * register @bf000000), memory mapping is disabled and the SPI registers
41 * are exposed to the CPU instead:
42 * bf000000 SPI_FUNCTION_SELECT
43 * bf000004 SPI_CONTROL
44 * bf000008 SPI_IO_CONTROL
45 * bf00000c SPI_READ_DATA
47 * When not memory-mapped, the SPI interface is essentially bitbanged
48 * using SPI_CONTROL and SPI_IO_CONTROL with the only hardware-assistance
49 * being the 32bit read-only shift-register SPI_READ_DATA.
58 #include <jtag/jtag.h>
59 #include <helper/time_support.h>
60 #include <helper/types.h>
61 #include <target/mips32.h>
62 #include <target/mips32_pracc.h>
63 #include <target/target.h>
65 #define BITS_PER_BYTE 8
67 #define ATH79_REG_FS 0
68 #define ATH79_REG_CLOCK 4
69 #define ATH79_REG_WRITE 8
70 #define ATH79_REG_DATA 12
72 #define ATH79_SPI_CS_ALLHI 0x70000
73 #define ATH79_SPI_CS0_HI 0x10000
74 #define ATH79_SPI_CS1_HI 0x20000
75 #define ATH79_SPI_CS2_HI 0x40000
76 #define ATH79_SPI_CE_HI 0x00100
77 #define ATH79_SPI_DO_HI 0x00001
79 #define ATH79_XFER_FINAL 0x00000001
80 #define ATH79_XFER_PARTIAL 0x00000000
83 #define ATH79_MAX_TIMEOUT (3000)
85 struct ath79_spi_ctx
{
91 struct ath79_flash_bank
{
95 const struct flash_device
*dev
;
96 struct ath79_spi_ctx spi
;
105 static const struct ath79_target target_devices
[] = {
106 /* name, tap_idcode, io_base */
107 { "ATH79", 0x00000001, 0xbf000000 },
111 static const uint32_t ath79_chipselects
[] = {
112 (~ATH79_SPI_CS0_HI
& ATH79_SPI_CS_ALLHI
),
113 (~ATH79_SPI_CS1_HI
& ATH79_SPI_CS_ALLHI
),
114 (~ATH79_SPI_CS2_HI
& ATH79_SPI_CS_ALLHI
),
117 static void ath79_pracc_addn(struct pracc_queue_info
*ctx
,
118 const uint32_t *instr
,
121 for (int i
= 0; i
< n
; i
++)
122 pracc_add(ctx
, 0, instr
[i
]);
125 static int ath79_spi_bitbang_codegen(struct ath79_flash_bank
*ath79_info
,
126 struct pracc_queue_info
*ctx
,
127 uint8_t *data
, int len
,
130 uint32_t cs_high
= ATH79_SPI_CS_ALLHI
;
131 uint32_t cs_low
= ath79_chipselects
[ath79_info
->chipselect
];
132 uint32_t clock_high
= cs_low
| ATH79_SPI_CE_HI
;
133 uint32_t clock_low
= cs_low
;
134 uint32_t pracc_out
= 0;
135 uint32_t io_base
= ath79_info
->io_base
;
137 const uint32_t preamble1
[] = {
138 /* $15 = MIPS32_PRACC_BASE_ADDR */
139 MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR
),
141 MIPS32_LUI(0, 1, UPPER16(io_base
)),
143 ath79_pracc_addn(ctx
, preamble1
, ARRAY_SIZE(preamble1
));
144 if (ath79_info
->spi
.pre_deselect
) {
145 /* Clear deselect flag so we don't deselect again if
146 * this is a partial xfer.
148 ath79_info
->spi
.pre_deselect
= 0;
149 const uint32_t pre_deselect
[] = {
150 /* [$1 + FS] = 1 (enable flash io register access) */
151 MIPS32_LUI(0, 2, UPPER16(1)),
152 MIPS32_ORI(0, 2, 2, LOWER16(1)),
153 MIPS32_SW(0, 2, ATH79_REG_FS
, 1),
154 /* deselect flash just in case */
155 /* $2 = SPI_CS_DIS */
156 MIPS32_LUI(0, 2, UPPER16(cs_high
)),
157 MIPS32_ORI(0, 2, 2, LOWER16(cs_high
)),
158 /* [$1 + WRITE] = $2 */
159 MIPS32_SW(0, 2, ATH79_REG_WRITE
, 1),
161 ath79_pracc_addn(ctx
, pre_deselect
, ARRAY_SIZE(pre_deselect
));
163 const uint32_t preamble2
[] = {
164 /* t0 = CLOCK_LOW + 0-bit */
165 MIPS32_LUI(0, 8, UPPER16((clock_low
+ 0))),
166 MIPS32_ORI(0, 8, 8, LOWER16((clock_low
+ 0))),
167 /* t1 = CLOCK_LOW + 1-bit */
168 MIPS32_LUI(0, 9, UPPER16((clock_low
+ 1))),
169 MIPS32_ORI(0, 9, 9, LOWER16((clock_low
+ 1))),
170 /* t2 = CLOCK_HIGH + 0-bit */
171 MIPS32_LUI(0, 10, UPPER16((clock_high
+ 0))),
172 MIPS32_ORI(0, 10, 10, LOWER16((clock_high
+ 0))),
173 /* t3 = CLOCK_HIGH + 1-bit */
174 MIPS32_LUI(0, 11, UPPER16((clock_high
+ 1))),
175 MIPS32_ORI(0, 11, 11, LOWER16((clock_high
+ 1))),
177 ath79_pracc_addn(ctx
, preamble2
, ARRAY_SIZE(preamble2
));
179 for (int i
= 0; i
< len
; i
++) {
182 /* Generate bitbang code for one byte, highest bit first .*/
183 for (int j
= BITS_PER_BYTE
- 1; j
>= 0; j
--) {
184 int bit
= ((x
>> j
) & 1);
187 /* [$1 + WRITE] = t1 */
189 MIPS32_SW(0, 9, ATH79_REG_WRITE
, 1));
190 /* [$1 + WRITE] = t3 */
192 MIPS32_SW(0, 11, ATH79_REG_WRITE
, 1));
194 /* [$1 + WRITE] = t0 */
196 MIPS32_SW(0, 8, ATH79_REG_WRITE
, 1));
197 /* [$1 + WRITE] = t2 */
199 MIPS32_SW(0, 10, ATH79_REG_WRITE
, 1));
203 /* $3 = [$1 + DATA] */
204 pracc_add(ctx
, 0, MIPS32_LW(0, 3, ATH79_REG_DATA
, 1));
206 pracc_add(ctx
, MIPS32_PRACC_PARAM_OUT
+ pracc_out
,
207 MIPS32_SW(0, 3, PRACC_OUT_OFFSET
+
212 if (len
& 3) { /* not a multiple of 4 bytes */
213 /* $3 = [$1 + DATA] */
214 pracc_add(ctx
, 0, MIPS32_LW(0, 3, ATH79_REG_DATA
, 1));
216 pracc_add(ctx
, MIPS32_PRACC_PARAM_OUT
+ pracc_out
,
217 MIPS32_SW(0, 3, PRACC_OUT_OFFSET
+ pracc_out
, 15));
221 if (ath79_info
->spi
.post_deselect
&& !partial_xfer
) {
222 const uint32_t post_deselect
[] = {
223 /* $2 = SPI_CS_DIS */
224 MIPS32_LUI(0, 2, UPPER16(cs_high
)),
225 MIPS32_ORI(0, 2, 2, LOWER16(cs_high
)),
226 /* [$1 + WRITE] = $2 */
227 MIPS32_SW(0, 2, ATH79_REG_WRITE
, 1),
229 /* [$1 + FS] = 0 (disable flash io register access) */
230 MIPS32_XORI(0, 2, 2, 0),
231 MIPS32_SW(0, 2, ATH79_REG_FS
, 1),
233 ath79_pracc_addn(ctx
, post_deselect
, ARRAY_SIZE(post_deselect
));
236 /* common pracc epilogue */
238 pracc_add(ctx
, 0, MIPS32_B(0, NEG16(ctx
->code_count
+ 1)));
239 /* restore $15 from DeSave */
240 pracc_add(ctx
, 0, MIPS32_MFC0(0, 15, 31, 0));
242 return pracc_out
/ 4;
245 static int ath79_spi_bitbang_chunk(struct flash_bank
*bank
,
246 uint8_t *data
, int len
, int *transferred
)
248 struct target
*target
= bank
->target
;
249 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
250 struct mips32_common
*mips32
= target_to_mips32(target
);
251 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
255 * These constants must match the worst case in the above code
256 * generator function ath79_spi_bitbang_codegen.
258 const int pracc_pre_post
= 26;
259 const int pracc_loop_byte
= 8 * 2 + 2;
261 struct pracc_queue_info ctx
= {
262 .ejtag_info
= ejtag_info
264 int max_len
= (PRACC_MAX_INSTRUCTIONS
- pracc_pre_post
) / pracc_loop_byte
;
265 int to_xfer
= len
> max_len
? max_len
: len
;
266 int partial_xfer
= len
!= to_xfer
;
267 int padded_len
= (to_xfer
+ 3) & ~3;
268 uint32_t *out
= malloc(padded_len
);
271 LOG_ERROR("not enough memory");
276 pracc_queue_init(&ctx
);
278 LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
279 target
, ath79_info
->io_base
, data
, len
);
281 LOG_DEBUG("max code %d => max len %d. to_xfer %d",
282 PRACC_MAX_INSTRUCTIONS
, max_len
, to_xfer
);
284 pracc_words
= ath79_spi_bitbang_codegen(
285 ath79_info
, &ctx
, data
, to_xfer
, partial_xfer
);
287 LOG_DEBUG("Assembled %d instructions, %d stores",
288 ctx
.code_count
, ctx
.store_count
);
290 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, out
, 1);
291 if (ctx
.retval
!= ERROR_OK
)
294 if (to_xfer
& 3) { /* Not a multiple of 4 bytes. */
296 * Need to realign last word since we didn't shift the
299 int missed_bytes
= 4 - (to_xfer
& 3);
301 out
[pracc_words
- 1] <<= BITS_PER_BYTE
* missed_bytes
;
305 * pracc reads return uint32_t in host endianness, convert to
307 * Since we know the ATH79 target is big endian and the SPI
308 * shift register has the bytes in highest to lowest bit order,
309 * this will ensure correct memory byte order regardless of host
312 target_buffer_set_u32_array(target
, (uint8_t *)out
, pracc_words
, out
);
314 if (LOG_LEVEL_IS(LOG_LVL_DEBUG
)) {
315 for (int i
= 0; i
< to_xfer
; i
++) {
316 LOG_DEBUG("bitbang %02x => %02x",
317 data
[i
], ((uint8_t *)out
)[i
]);
320 memcpy(data
, out
, to_xfer
);
321 *transferred
= to_xfer
;
324 pracc_queue_free(&ctx
);
329 static void ath79_spi_bitbang_prepare(struct flash_bank
*bank
)
331 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
333 ath79_info
->spi
.pre_deselect
= 1;
336 static int ath79_spi_bitbang_bytes(struct flash_bank
*bank
,
337 uint8_t *data
, int len
, uint32_t flags
)
339 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
343 ath79_info
->spi
.post_deselect
= !!(flags
& ATH79_XFER_FINAL
);
347 retval
= ath79_spi_bitbang_chunk(
348 bank
, data
, len
, &transferred
);
349 if (retval
!= ERROR_OK
)
359 FLASH_BANK_COMMAND_HANDLER(ath79_flash_bank_command
)
361 struct ath79_flash_bank
*ath79_info
;
364 LOG_DEBUG("%s", __func__
);
366 if (CMD_ARGC
< 6 || CMD_ARGC
> 7)
367 return ERROR_COMMAND_SYNTAX_ERROR
;
370 if (strcmp(CMD_ARGV
[6], "cs0") == 0)
371 chipselect
= 0; /* default */
372 else if (strcmp(CMD_ARGV
[6], "cs1") == 0)
374 else if (strcmp(CMD_ARGV
[6], "cs2") == 0)
377 LOG_ERROR("Unknown arg: %s", CMD_ARGV
[6]);
378 return ERROR_COMMAND_SYNTAX_ERROR
;
382 ath79_info
= calloc(1, sizeof(struct ath79_flash_bank
));
384 LOG_ERROR("not enough memory");
388 ath79_info
->chipselect
= chipselect
;
389 bank
->driver_priv
= ath79_info
;
394 /* Read the status register of the external SPI flash chip. */
395 static int read_status_reg(struct flash_bank
*bank
, uint32_t *status
)
397 uint8_t spi_bytes
[] = {SPIFLASH_READ_STATUS
, 0};
400 /* Send SPI command "read STATUS" */
401 ath79_spi_bitbang_prepare(bank
);
402 retval
= ath79_spi_bitbang_bytes(
403 bank
, spi_bytes
, sizeof(spi_bytes
),
406 *status
= spi_bytes
[1];
411 /* check for WIP (write in progress) bit in status register */
413 static int wait_till_ready(struct flash_bank
*bank
, int timeout
)
419 endtime
= timeval_ms() + timeout
;
421 /* read flash status register */
422 retval
= read_status_reg(bank
, &status
);
423 if (retval
!= ERROR_OK
)
426 if ((status
& SPIFLASH_BSY_BIT
) == 0)
429 } while (timeval_ms() < endtime
);
431 LOG_ERROR("timeout");
435 /* Send "write enable" command to SPI flash chip. */
436 static int ath79_write_enable(struct flash_bank
*bank
)
441 uint8_t spi_bytes
[] = {SPIFLASH_WRITE_ENABLE
};
443 /* Send SPI command "write enable" */
444 ath79_spi_bitbang_prepare(bank
);
445 retval
= ath79_spi_bitbang_bytes(
446 bank
, spi_bytes
, sizeof(spi_bytes
),
448 if (retval
!= ERROR_OK
)
451 /* read flash status register */
452 retval
= read_status_reg(bank
, &status
);
453 if (retval
!= ERROR_OK
)
456 /* Check write enabled */
457 if ((status
& SPIFLASH_WE_BIT
) == 0) {
458 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32
,
466 static int erase_command(struct flash_bank
*bank
, int sector
)
468 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
469 uint32_t offset
= bank
->sectors
[sector
].offset
;
471 uint8_t spi_bytes
[] = {
472 ath79_info
->dev
->erase_cmd
,
478 /* bitbang command */
479 ath79_spi_bitbang_prepare(bank
);
480 return ath79_spi_bitbang_bytes(
481 bank
, spi_bytes
, sizeof(spi_bytes
),
485 static int ath79_erase_sector(struct flash_bank
*bank
, int sector
)
487 int retval
= ath79_write_enable(bank
);
489 if (retval
!= ERROR_OK
)
492 /* send SPI command "block erase" */
493 retval
= erase_command(bank
, sector
);
494 if (retval
!= ERROR_OK
)
497 /* poll WIP for end of self timed Sector Erase cycle */
498 return wait_till_ready(bank
, ATH79_MAX_TIMEOUT
);
501 static int ath79_erase(struct flash_bank
*bank
, int first
, int last
)
503 struct target
*target
= bank
->target
;
504 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
505 int retval
= ERROR_OK
;
508 LOG_DEBUG("%s: from sector %d to sector %d", __func__
, first
, last
);
510 if (target
->state
!= TARGET_HALTED
) {
511 LOG_ERROR("Target not halted");
512 return ERROR_TARGET_NOT_HALTED
;
515 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
)) {
516 LOG_ERROR("Flash sector invalid");
517 return ERROR_FLASH_SECTOR_INVALID
;
520 if (!ath79_info
->probed
) {
521 LOG_ERROR("Flash bank not probed");
522 return ERROR_FLASH_BANK_NOT_PROBED
;
525 for (sector
= first
; sector
<= last
; sector
++) {
526 if (bank
->sectors
[sector
].is_protected
) {
527 LOG_ERROR("Flash sector %d protected", sector
);
532 for (sector
= first
; sector
<= last
; sector
++) {
533 retval
= ath79_erase_sector(bank
, sector
);
534 if (retval
!= ERROR_OK
)
542 static int ath79_protect(struct flash_bank
*bank
, int set
,
547 for (sector
= first
; sector
<= last
; sector
++)
548 bank
->sectors
[sector
].is_protected
= set
;
552 static int ath79_write_page(struct flash_bank
*bank
, const uint8_t *buffer
,
553 uint32_t address
, uint32_t len
)
555 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
556 uint8_t spi_bytes
[] = {
557 SPIFLASH_PAGE_PROGRAM
,
565 if (address
& 0xff) {
566 LOG_ERROR("ath79_write_page: unaligned write address: %08x",
570 if (!ath79_info
->spi
.page_buf
) {
571 LOG_ERROR("ath79_write_page: page buffer not initialized");
574 if (len
> ath79_info
->dev
->pagesize
) {
575 LOG_ERROR("ath79_write_page: len bigger than page size %d: %d",
576 ath79_info
->dev
->pagesize
, len
);
580 for (i
= 0; i
< len
; i
++) {
581 if (buffer
[i
] != 0xff)
584 if (i
== len
) /* all 0xff, no need to program. */
587 LOG_INFO("writing %d bytes to flash page @0x%08x", len
, address
);
589 memcpy(ath79_info
->spi
.page_buf
, buffer
, len
);
592 retval
= ath79_write_enable(bank
);
593 if (retval
!= ERROR_OK
)
596 /* bitbang command */
597 ath79_spi_bitbang_prepare(bank
);
598 retval
= ath79_spi_bitbang_bytes(
599 bank
, spi_bytes
, sizeof(spi_bytes
),
601 if (retval
!= ERROR_OK
)
605 return ath79_spi_bitbang_bytes(
606 bank
, ath79_info
->spi
.page_buf
, len
,
610 static int ath79_write_buffer(struct flash_bank
*bank
, const uint8_t *buffer
,
611 uint32_t address
, uint32_t len
)
613 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
614 const uint32_t page_size
= ath79_info
->dev
->pagesize
;
617 LOG_DEBUG("%s: address=0x%08" PRIx32
" len=0x%08" PRIx32
,
618 __func__
, address
, len
);
621 int page_len
= len
> page_size
? page_size
: len
;
623 retval
= ath79_write_page(
624 bank
, buffer
, address
, page_len
);
625 if (retval
!= ERROR_OK
)
629 address
+= page_size
;
636 static int ath79_write(struct flash_bank
*bank
, const uint8_t *buffer
,
637 uint32_t offset
, uint32_t count
)
639 struct target
*target
= bank
->target
;
642 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
643 __func__
, offset
, count
);
645 if (offset
< bank
->base
|| offset
>= bank
->base
+ bank
->size
) {
646 LOG_ERROR("Start address out of range");
650 offset
-= bank
->base
;
652 if (target
->state
!= TARGET_HALTED
) {
653 LOG_ERROR("Target not halted");
654 return ERROR_TARGET_NOT_HALTED
;
657 if (offset
+ count
> bank
->size
) {
658 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
659 count
= bank
->size
- offset
;
662 /* Check sector protection */
663 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
664 /* Start offset in or before this sector? */
665 /* End offset in or behind this sector? */
666 struct flash_sector
*bs
= &bank
->sectors
[sector
];
668 if ((offset
< (bs
->offset
+ bs
->size
)) &&
669 ((offset
+ count
- 1) >= bs
->offset
) &&
671 LOG_ERROR("Flash sector %d protected", sector
);
676 return ath79_write_buffer(bank
, buffer
, offset
, count
);
679 static int ath79_read_buffer(struct flash_bank
*bank
, uint8_t *buffer
,
680 uint32_t address
, uint32_t len
)
682 uint8_t spi_bytes
[] = {
690 LOG_DEBUG("%s: address=0x%08" PRIx32
" len=0x%08" PRIx32
,
691 __func__
, address
, len
);
693 if (address
& 0xff) {
694 LOG_ERROR("ath79_read_buffer: unaligned read address: %08x",
699 LOG_INFO("reading %d bytes from flash @0x%08x", len
, address
);
701 /* bitbang command */
702 ath79_spi_bitbang_prepare(bank
);
703 retval
= ath79_spi_bitbang_bytes(
704 bank
, spi_bytes
, sizeof(spi_bytes
), ATH79_XFER_PARTIAL
);
705 if (retval
!= ERROR_OK
)
709 return ath79_spi_bitbang_bytes(
710 bank
, buffer
, len
, ATH79_XFER_FINAL
);
713 static int ath79_read(struct flash_bank
*bank
, uint8_t *buffer
,
714 uint32_t offset
, uint32_t count
)
716 struct target
*target
= bank
->target
;
718 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
719 __func__
, offset
, count
);
721 if (offset
< bank
->base
|| offset
>= bank
->base
+ bank
->size
) {
722 LOG_ERROR("Start address out of range");
726 offset
-= bank
->base
;
728 if (target
->state
!= TARGET_HALTED
) {
729 LOG_ERROR("Target not halted");
730 return ERROR_TARGET_NOT_HALTED
;
733 if (offset
+ count
> bank
->size
) {
734 LOG_WARNING("Reads past end of flash. Extra data discarded.");
735 count
= bank
->size
- offset
;
738 return ath79_read_buffer(bank
, buffer
, offset
, count
);
741 /* Return ID of flash device */
742 static int read_flash_id(struct flash_bank
*bank
, uint32_t *id
)
744 struct target
*target
= bank
->target
;
746 uint8_t spi_bytes
[] = {SPIFLASH_READ_ID
, 0, 0, 0};
748 if (target
->state
!= TARGET_HALTED
) {
749 LOG_ERROR("Target not halted");
750 return ERROR_TARGET_NOT_HALTED
;
753 /* Send SPI command "read ID" */
754 ath79_spi_bitbang_prepare(bank
);
755 retval
= ath79_spi_bitbang_bytes(
756 bank
, spi_bytes
, sizeof(spi_bytes
), ATH79_XFER_FINAL
);
757 if (retval
!= ERROR_OK
)
760 *id
= (spi_bytes
[1] << 0)
761 | (spi_bytes
[2] << 8)
762 | (spi_bytes
[3] << 16);
764 if (*id
== 0xffffff) {
765 LOG_ERROR("No SPI flash found");
772 static int ath79_probe(struct flash_bank
*bank
)
774 struct target
*target
= bank
->target
;
775 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
776 struct flash_sector
*sectors
;
777 uint32_t id
= 0; /* silence uninitialized warning */
778 const struct ath79_target
*target_device
;
781 if (ath79_info
->probed
) {
783 free(ath79_info
->spi
.page_buf
);
785 ath79_info
->probed
= 0;
787 for (target_device
= target_devices
; target_device
->name
;
789 if (target_device
->tap_idcode
== target
->tap
->idcode
)
791 if (!target_device
->name
) {
792 LOG_ERROR("Device ID 0x%" PRIx32
" is not known",
793 target
->tap
->idcode
);
797 ath79_info
->io_base
= target_device
->io_base
;
799 LOG_DEBUG("Found device %s at address 0x%" PRIx32
,
800 target_device
->name
, bank
->base
);
802 retval
= read_flash_id(bank
, &id
);
803 if (retval
!= ERROR_OK
)
806 ath79_info
->dev
= NULL
;
807 for (const struct flash_device
*p
= flash_devices
; p
->name
; p
++)
808 if (p
->device_id
== id
) {
813 if (!ath79_info
->dev
) {
814 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32
")", id
);
818 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32
")",
819 ath79_info
->dev
->name
, ath79_info
->dev
->device_id
);
821 /* Set correct size value */
822 bank
->size
= ath79_info
->dev
->size_in_bytes
;
824 /* create and fill sectors array */
826 ath79_info
->dev
->size_in_bytes
/ ath79_info
->dev
->sectorsize
;
827 sectors
= calloc(1, sizeof(struct flash_sector
) * bank
->num_sectors
);
829 LOG_ERROR("not enough memory");
832 ath79_info
->spi
.page_buf
= malloc(ath79_info
->dev
->pagesize
);
833 if (!ath79_info
->spi
.page_buf
) {
834 LOG_ERROR("not enough memory");
839 for (int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
840 sectors
[sector
].offset
= sector
* ath79_info
->dev
->sectorsize
;
841 sectors
[sector
].size
= ath79_info
->dev
->sectorsize
;
842 sectors
[sector
].is_erased
= 0;
843 sectors
[sector
].is_protected
= 1;
846 bank
->sectors
= sectors
;
847 ath79_info
->probed
= 1;
851 static int ath79_auto_probe(struct flash_bank
*bank
)
853 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
855 if (ath79_info
->probed
)
857 return ath79_probe(bank
);
860 static int ath79_flash_blank_check(struct flash_bank
*bank
)
862 /* Not implemented */
866 static int ath79_protect_check(struct flash_bank
*bank
)
868 /* Not implemented */
872 static int get_ath79_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
874 struct ath79_flash_bank
*ath79_info
= bank
->driver_priv
;
876 if (!ath79_info
->probed
) {
877 snprintf(buf
, buf_size
,
878 "\nATH79 flash bank not probed yet\n");
882 snprintf(buf
, buf_size
, "\nATH79 flash information:\n"
883 " Device \'%s\' (ID 0x%08" PRIx32
")\n",
884 ath79_info
->dev
->name
, ath79_info
->dev
->device_id
);
889 struct flash_driver ath79_flash
= {
891 .flash_bank_command
= ath79_flash_bank_command
,
892 .erase
= ath79_erase
,
893 .protect
= ath79_protect
,
894 .write
= ath79_write
,
896 .probe
= ath79_probe
,
897 .auto_probe
= ath79_auto_probe
,
898 .erase_check
= ath79_flash_blank_check
,
899 .protect_check
= ath79_protect_check
,
900 .info
= get_ath79_info
,
901 .free_driver_priv
= default_flash_free_driver_priv
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)