arm_adi_v5: Split CSW bits into AHB/APB/AXI
[openocd.git] / src / flash / nor / ath79.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Tobias Diedrich *
3 * <ranma+openwrt@tdiedrich.de> *
4 * *
5 * based on the stmsmi code written by Antonio Borneo *
6 * <borneo.antonio@gmail.com> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc. *
21 * *
22 ***************************************************************************/
23 /*
24 * Driver for the Atheros AR7xxx/AR9xxx SPI flash interface.
25 *
26 * Since no SPI mode register is present, presumably only
27 * SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
28 *
29 * The SPI interface supports up to 3 chip selects, however the SPI flash
30 * used for booting the system must be connected to CS0.
31 *
32 * On boot, the first 4MiB of flash space are memory-mapped into the
33 * area bf000000 - bfffffff (4 copies), so the MIPS bootstrap
34 * vector bfc00000 is mapped to the beginning of the flash.
35 *
36 * By writing a 1 to the REMAP_DISABLE bit in the SPI_CONTROL register,
37 * the full area of 16MiB is mapped.
38 *
39 * By writing a 0 to the SPI_FUNCTION_SELECT register (write-only dword
40 * register @bf000000), memory mapping is disabled and the SPI registers
41 * are exposed to the CPU instead:
42 * bf000000 SPI_FUNCTION_SELECT
43 * bf000004 SPI_CONTROL
44 * bf000008 SPI_IO_CONTROL
45 * bf00000c SPI_READ_DATA
46 *
47 * When not memory-mapped, the SPI interface is essentially bitbanged
48 * using SPI_CONTROL and SPI_IO_CONTROL with the only hardware-assistance
49 * being the 32bit read-only shift-register SPI_READ_DATA.
50 */
51
52 #ifdef HAVE_CONFIG_H
53 #include "config.h"
54 #endif
55
56 #include "imp.h"
57 #include "spi.h"
58 #include <jtag/jtag.h>
59 #include <helper/time_support.h>
60 #include <helper/types.h>
61 #include <target/mips32.h>
62 #include <target/mips32_pracc.h>
63 #include <target/target.h>
64
65 #define BITS_PER_BYTE 8
66
67 #define ATH79_REG_FS 0
68 #define ATH79_REG_CLOCK 4
69 #define ATH79_REG_WRITE 8
70 #define ATH79_REG_DATA 12
71
72 #define ATH79_SPI_CS_ALLHI 0x70000
73 #define ATH79_SPI_CS0_HI 0x10000
74 #define ATH79_SPI_CS1_HI 0x20000
75 #define ATH79_SPI_CS2_HI 0x40000
76 #define ATH79_SPI_CE_HI 0x00100
77 #define ATH79_SPI_DO_HI 0x00001
78
79 #define ATH79_XFER_FINAL 0x00000001
80 #define ATH79_XFER_PARTIAL 0x00000000
81
82 /* Timeout in ms */
83 #define ATH79_MAX_TIMEOUT (3000)
84
85 struct ath79_spi_ctx {
86 uint8_t *page_buf;
87 int pre_deselect;
88 int post_deselect;
89 };
90
91 struct ath79_flash_bank {
92 int probed;
93 int chipselect;
94 uint32_t io_base;
95 const struct flash_device *dev;
96 struct ath79_spi_ctx spi;
97 };
98
99 struct ath79_target {
100 char *name;
101 uint32_t tap_idcode;
102 uint32_t io_base;
103 };
104
105 static const struct ath79_target target_devices[] = {
106 /* name, tap_idcode, io_base */
107 { "ATH79", 0x00000001, 0xbf000000 },
108 { NULL, 0, 0 }
109 };
110
111 static const uint32_t ath79_chipselects[] = {
112 (~ATH79_SPI_CS0_HI & ATH79_SPI_CS_ALLHI),
113 (~ATH79_SPI_CS1_HI & ATH79_SPI_CS_ALLHI),
114 (~ATH79_SPI_CS2_HI & ATH79_SPI_CS_ALLHI),
115 };
116
117 static void ath79_pracc_addn(struct pracc_queue_info *ctx,
118 const uint32_t *instr,
119 int n)
120 {
121 for (int i = 0; i < n; i++)
122 pracc_add(ctx, 0, instr[i]);
123 }
124
125 static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
126 struct pracc_queue_info *ctx,
127 uint8_t *data, int len,
128 int partial_xfer)
129 {
130 uint32_t cs_high = ATH79_SPI_CS_ALLHI;
131 uint32_t cs_low = ath79_chipselects[ath79_info->chipselect];
132 uint32_t clock_high = cs_low | ATH79_SPI_CE_HI;
133 uint32_t clock_low = cs_low;
134 uint32_t pracc_out = 0;
135 uint32_t io_base = ath79_info->io_base;
136
137 const uint32_t preamble1[] = {
138 /* $15 = MIPS32_PRACC_BASE_ADDR */
139 MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR),
140 /* $1 = io_base */
141 MIPS32_LUI(0, 1, UPPER16(io_base)),
142 };
143 ath79_pracc_addn(ctx, preamble1, ARRAY_SIZE(preamble1));
144 if (ath79_info->spi.pre_deselect) {
145 /* Clear deselect flag so we don't deselect again if
146 * this is a partial xfer.
147 */
148 ath79_info->spi.pre_deselect = 0;
149 const uint32_t pre_deselect[] = {
150 /* [$1 + FS] = 1 (enable flash io register access) */
151 MIPS32_LUI(0, 2, UPPER16(1)),
152 MIPS32_ORI(0, 2, 2, LOWER16(1)),
153 MIPS32_SW(0, 2, ATH79_REG_FS, 1),
154 /* deselect flash just in case */
155 /* $2 = SPI_CS_DIS */
156 MIPS32_LUI(0, 2, UPPER16(cs_high)),
157 MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
158 /* [$1 + WRITE] = $2 */
159 MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
160 };
161 ath79_pracc_addn(ctx, pre_deselect, ARRAY_SIZE(pre_deselect));
162 }
163 const uint32_t preamble2[] = {
164 /* t0 = CLOCK_LOW + 0-bit */
165 MIPS32_LUI(0, 8, UPPER16((clock_low + 0))),
166 MIPS32_ORI(0, 8, 8, LOWER16((clock_low + 0))),
167 /* t1 = CLOCK_LOW + 1-bit */
168 MIPS32_LUI(0, 9, UPPER16((clock_low + 1))),
169 MIPS32_ORI(0, 9, 9, LOWER16((clock_low + 1))),
170 /* t2 = CLOCK_HIGH + 0-bit */
171 MIPS32_LUI(0, 10, UPPER16((clock_high + 0))),
172 MIPS32_ORI(0, 10, 10, LOWER16((clock_high + 0))),
173 /* t3 = CLOCK_HIGH + 1-bit */
174 MIPS32_LUI(0, 11, UPPER16((clock_high + 1))),
175 MIPS32_ORI(0, 11, 11, LOWER16((clock_high + 1))),
176 };
177 ath79_pracc_addn(ctx, preamble2, ARRAY_SIZE(preamble2));
178
179 for (int i = 0; i < len; i++) {
180 uint8_t x = data[i];
181
182 /* Generate bitbang code for one byte, highest bit first .*/
183 for (int j = BITS_PER_BYTE - 1; j >= 0; j--) {
184 int bit = ((x >> j) & 1);
185
186 if (bit) {
187 /* [$1 + WRITE] = t1 */
188 pracc_add(ctx, 0,
189 MIPS32_SW(0, 9, ATH79_REG_WRITE, 1));
190 /* [$1 + WRITE] = t3 */
191 pracc_add(ctx, 0,
192 MIPS32_SW(0, 11, ATH79_REG_WRITE, 1));
193 } else {
194 /* [$1 + WRITE] = t0 */
195 pracc_add(ctx, 0,
196 MIPS32_SW(0, 8, ATH79_REG_WRITE, 1));
197 /* [$1 + WRITE] = t2 */
198 pracc_add(ctx, 0,
199 MIPS32_SW(0, 10, ATH79_REG_WRITE, 1));
200 }
201 }
202 if (i % 4 == 3) {
203 /* $3 = [$1 + DATA] */
204 pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
205 /* [OUTi] = $3 */
206 pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
207 MIPS32_SW(0, 3, PRACC_OUT_OFFSET +
208 pracc_out, 15));
209 pracc_out += 4;
210 }
211 }
212 if (len & 3) { /* not a multiple of 4 bytes */
213 /* $3 = [$1 + DATA] */
214 pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
215 /* [OUTi] = $3 */
216 pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
217 MIPS32_SW(0, 3, PRACC_OUT_OFFSET + pracc_out, 15));
218 pracc_out += 4;
219 }
220
221 if (ath79_info->spi.post_deselect && !partial_xfer) {
222 const uint32_t post_deselect[] = {
223 /* $2 = SPI_CS_DIS */
224 MIPS32_LUI(0, 2, UPPER16(cs_high)),
225 MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
226 /* [$1 + WRITE] = $2 */
227 MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
228
229 /* [$1 + FS] = 0 (disable flash io register access) */
230 MIPS32_XORI(0, 2, 2, 0),
231 MIPS32_SW(0, 2, ATH79_REG_FS, 1),
232 };
233 ath79_pracc_addn(ctx, post_deselect, ARRAY_SIZE(post_deselect));
234 }
235
236 /* common pracc epilogue */
237 /* jump to start */
238 pracc_add(ctx, 0, MIPS32_B(0, NEG16(ctx->code_count + 1)));
239 /* restore $15 from DeSave */
240 pracc_add(ctx, 0, MIPS32_MFC0(0, 15, 31, 0));
241
242 return pracc_out / 4;
243 }
244
245 static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
246 uint8_t *data, int len, int *transferred)
247 {
248 struct target *target = bank->target;
249 struct ath79_flash_bank *ath79_info = bank->driver_priv;
250 struct mips32_common *mips32 = target_to_mips32(target);
251 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
252 int pracc_words;
253
254 /*
255 * These constants must match the worst case in the above code
256 * generator function ath79_spi_bitbang_codegen.
257 */
258 const int pracc_pre_post = 26;
259 const int pracc_loop_byte = 8 * 2 + 2;
260
261 struct pracc_queue_info ctx = {
262 .ejtag_info = ejtag_info
263 };
264 int max_len = (PRACC_MAX_INSTRUCTIONS - pracc_pre_post) / pracc_loop_byte;
265 int to_xfer = len > max_len ? max_len : len;
266 int partial_xfer = len != to_xfer;
267 int padded_len = (to_xfer + 3) & ~3;
268 uint32_t *out = malloc(padded_len);
269
270 if (!out) {
271 LOG_ERROR("not enough memory");
272 return ERROR_FAIL;
273 }
274
275 *transferred = 0;
276 pracc_queue_init(&ctx);
277
278 LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
279 target, ath79_info->io_base, data, len);
280
281 LOG_DEBUG("max code %d => max len %d. to_xfer %d",
282 PRACC_MAX_INSTRUCTIONS, max_len, to_xfer);
283
284 pracc_words = ath79_spi_bitbang_codegen(
285 ath79_info, &ctx, data, to_xfer, partial_xfer);
286
287 LOG_DEBUG("Assembled %d instructions, %d stores",
288 ctx.code_count, ctx.store_count);
289
290 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out, 1);
291 if (ctx.retval != ERROR_OK)
292 goto exit;
293
294 if (to_xfer & 3) { /* Not a multiple of 4 bytes. */
295 /*
296 * Need to realign last word since we didn't shift the
297 * full 32 bits.
298 */
299 int missed_bytes = 4 - (to_xfer & 3);
300
301 out[pracc_words - 1] <<= BITS_PER_BYTE * missed_bytes;
302 }
303
304 /*
305 * pracc reads return uint32_t in host endianness, convert to
306 * target endianness.
307 * Since we know the ATH79 target is big endian and the SPI
308 * shift register has the bytes in highest to lowest bit order,
309 * this will ensure correct memory byte order regardless of host
310 * endianness.
311 */
312 target_buffer_set_u32_array(target, (uint8_t *)out, pracc_words, out);
313
314 if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) {
315 for (int i = 0; i < to_xfer; i++) {
316 LOG_DEBUG("bitbang %02x => %02x",
317 data[i], ((uint8_t *)out)[i]);
318 }
319 }
320 memcpy(data, out, to_xfer);
321 *transferred = to_xfer;
322
323 exit:
324 pracc_queue_free(&ctx);
325 free(out);
326 return ctx.retval;
327 }
328
329 static void ath79_spi_bitbang_prepare(struct flash_bank *bank)
330 {
331 struct ath79_flash_bank *ath79_info = bank->driver_priv;
332
333 ath79_info->spi.pre_deselect = 1;
334 }
335
336 static int ath79_spi_bitbang_bytes(struct flash_bank *bank,
337 uint8_t *data, int len, uint32_t flags)
338 {
339 struct ath79_flash_bank *ath79_info = bank->driver_priv;
340 int retval;
341 int transferred;
342
343 ath79_info->spi.post_deselect = !!(flags & ATH79_XFER_FINAL);
344
345 do {
346 transferred = 0;
347 retval = ath79_spi_bitbang_chunk(
348 bank, data, len, &transferred);
349 if (retval != ERROR_OK)
350 return retval;
351
352 data += transferred;
353 len -= transferred;
354 } while (len > 0);
355
356 return ERROR_OK;
357 }
358
359 FLASH_BANK_COMMAND_HANDLER(ath79_flash_bank_command)
360 {
361 struct ath79_flash_bank *ath79_info;
362 int chipselect = 0;
363
364 LOG_DEBUG("%s", __func__);
365
366 if (CMD_ARGC < 6 || CMD_ARGC > 7)
367 return ERROR_COMMAND_SYNTAX_ERROR;
368
369 if (CMD_ARGC == 7) {
370 if (strcmp(CMD_ARGV[6], "cs0") == 0)
371 chipselect = 0; /* default */
372 else if (strcmp(CMD_ARGV[6], "cs1") == 0)
373 chipselect = 1;
374 else if (strcmp(CMD_ARGV[6], "cs2") == 0)
375 chipselect = 2;
376 else {
377 LOG_ERROR("Unknown arg: %s", CMD_ARGV[6]);
378 return ERROR_COMMAND_SYNTAX_ERROR;
379 }
380 }
381
382 ath79_info = calloc(1, sizeof(struct ath79_flash_bank));
383 if (!ath79_info) {
384 LOG_ERROR("not enough memory");
385 return ERROR_FAIL;
386 }
387
388 ath79_info->chipselect = chipselect;
389 bank->driver_priv = ath79_info;
390
391 return ERROR_OK;
392 }
393
394 /* Read the status register of the external SPI flash chip. */
395 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
396 {
397 uint8_t spi_bytes[] = {SPIFLASH_READ_STATUS, 0};
398 int retval;
399
400 /* Send SPI command "read STATUS" */
401 ath79_spi_bitbang_prepare(bank);
402 retval = ath79_spi_bitbang_bytes(
403 bank, spi_bytes, sizeof(spi_bytes),
404 ATH79_XFER_FINAL);
405
406 *status = spi_bytes[1];
407
408 return retval;
409 }
410
411 /* check for WIP (write in progress) bit in status register */
412 /* timeout in ms */
413 static int wait_till_ready(struct flash_bank *bank, int timeout)
414 {
415 uint32_t status;
416 int retval;
417 long long endtime;
418
419 endtime = timeval_ms() + timeout;
420 do {
421 /* read flash status register */
422 retval = read_status_reg(bank, &status);
423 if (retval != ERROR_OK)
424 return retval;
425
426 if ((status & SPIFLASH_BSY_BIT) == 0)
427 return ERROR_OK;
428 alive_sleep(1);
429 } while (timeval_ms() < endtime);
430
431 LOG_ERROR("timeout");
432 return ERROR_FAIL;
433 }
434
435 /* Send "write enable" command to SPI flash chip. */
436 static int ath79_write_enable(struct flash_bank *bank)
437 {
438 uint32_t status;
439 int retval;
440
441 uint8_t spi_bytes[] = {SPIFLASH_WRITE_ENABLE};
442
443 /* Send SPI command "write enable" */
444 ath79_spi_bitbang_prepare(bank);
445 retval = ath79_spi_bitbang_bytes(
446 bank, spi_bytes, sizeof(spi_bytes),
447 ATH79_XFER_FINAL);
448 if (retval != ERROR_OK)
449 return retval;
450
451 /* read flash status register */
452 retval = read_status_reg(bank, &status);
453 if (retval != ERROR_OK)
454 return retval;
455
456 /* Check write enabled */
457 if ((status & SPIFLASH_WE_BIT) == 0) {
458 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32,
459 status);
460 return ERROR_FAIL;
461 }
462
463 return ERROR_OK;
464 }
465
466 static int erase_command(struct flash_bank *bank, int sector)
467 {
468 struct ath79_flash_bank *ath79_info = bank->driver_priv;
469 uint32_t offset = bank->sectors[sector].offset;
470
471 uint8_t spi_bytes[] = {
472 ath79_info->dev->erase_cmd,
473 offset >> 16,
474 offset >> 8,
475 offset
476 };
477
478 /* bitbang command */
479 ath79_spi_bitbang_prepare(bank);
480 return ath79_spi_bitbang_bytes(
481 bank, spi_bytes, sizeof(spi_bytes),
482 ATH79_XFER_FINAL);
483 }
484
485 static int ath79_erase_sector(struct flash_bank *bank, int sector)
486 {
487 int retval = ath79_write_enable(bank);
488
489 if (retval != ERROR_OK)
490 return retval;
491
492 /* send SPI command "block erase" */
493 retval = erase_command(bank, sector);
494 if (retval != ERROR_OK)
495 return retval;
496
497 /* poll WIP for end of self timed Sector Erase cycle */
498 return wait_till_ready(bank, ATH79_MAX_TIMEOUT);
499 }
500
501 static int ath79_erase(struct flash_bank *bank, int first, int last)
502 {
503 struct target *target = bank->target;
504 struct ath79_flash_bank *ath79_info = bank->driver_priv;
505 int retval = ERROR_OK;
506 int sector;
507
508 LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
509
510 if (target->state != TARGET_HALTED) {
511 LOG_ERROR("Target not halted");
512 return ERROR_TARGET_NOT_HALTED;
513 }
514
515 if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
516 LOG_ERROR("Flash sector invalid");
517 return ERROR_FLASH_SECTOR_INVALID;
518 }
519
520 if (!ath79_info->probed) {
521 LOG_ERROR("Flash bank not probed");
522 return ERROR_FLASH_BANK_NOT_PROBED;
523 }
524
525 if (ath79_info->dev->erase_cmd == 0x00)
526 return ERROR_FLASH_OPER_UNSUPPORTED;
527
528 for (sector = first; sector <= last; sector++) {
529 if (bank->sectors[sector].is_protected) {
530 LOG_ERROR("Flash sector %d protected", sector);
531 return ERROR_FAIL;
532 }
533 }
534
535 for (sector = first; sector <= last; sector++) {
536 retval = ath79_erase_sector(bank, sector);
537 if (retval != ERROR_OK)
538 break;
539 keep_alive();
540 }
541
542 return retval;
543 }
544
545 static int ath79_protect(struct flash_bank *bank, int set,
546 int first, int last)
547 {
548 int sector;
549
550 for (sector = first; sector <= last; sector++)
551 bank->sectors[sector].is_protected = set;
552 return ERROR_OK;
553 }
554
555 static int ath79_write_page(struct flash_bank *bank, const uint8_t *buffer,
556 uint32_t address, uint32_t len)
557 {
558 struct ath79_flash_bank *ath79_info = bank->driver_priv;
559 uint8_t spi_bytes[] = {
560 SPIFLASH_PAGE_PROGRAM,
561 address >> 16,
562 address >> 8,
563 address,
564 };
565 int retval;
566 uint32_t i, pagesize;
567
568 /* if no write pagesize, use reasonable default */
569 pagesize = ath79_info->dev->pagesize ?
570 ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
571
572 if (address & 0xff) {
573 LOG_ERROR("ath79_write_page: unaligned write address: %08x",
574 address);
575 return ERROR_FAIL;
576 }
577 if (!ath79_info->spi.page_buf) {
578 LOG_ERROR("ath79_write_page: page buffer not initialized");
579 return ERROR_FAIL;
580 }
581 if (len > ath79_info->dev->pagesize) {
582 LOG_ERROR("ath79_write_page: len bigger than page size %d: %d",
583 pagesize, len);
584 return ERROR_FAIL;
585 }
586
587 for (i = 0; i < len; i++) {
588 if (buffer[i] != 0xff)
589 break;
590 }
591 if (i == len) /* all 0xff, no need to program. */
592 return ERROR_OK;
593
594 LOG_INFO("writing %d bytes to flash page @0x%08x", len, address);
595
596 memcpy(ath79_info->spi.page_buf, buffer, len);
597
598 /* unlock writes */
599 retval = ath79_write_enable(bank);
600 if (retval != ERROR_OK)
601 return retval;
602
603 /* bitbang command */
604 ath79_spi_bitbang_prepare(bank);
605 retval = ath79_spi_bitbang_bytes(
606 bank, spi_bytes, sizeof(spi_bytes),
607 ATH79_XFER_PARTIAL);
608 if (retval != ERROR_OK)
609 return retval;
610
611 /* write data */
612 return ath79_spi_bitbang_bytes(
613 bank, ath79_info->spi.page_buf, len,
614 ATH79_XFER_FINAL);
615 }
616
617 static int ath79_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
618 uint32_t address, uint32_t len)
619 {
620 struct ath79_flash_bank *ath79_info = bank->driver_priv;
621 uint32_t page_size;
622 int retval;
623
624 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
625 __func__, address, len);
626
627 /* if no valid page_size, use reasonable default */
628 page_size = ath79_info->dev->pagesize ?
629 ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
630
631 while (len > 0) {
632 int page_len = len > page_size ? page_size : len;
633
634 retval = ath79_write_page(
635 bank, buffer, address, page_len);
636 if (retval != ERROR_OK)
637 return retval;
638
639 buffer += page_size;
640 address += page_size;
641 len -= page_len;
642 }
643
644 return ERROR_OK;
645 }
646
647 static int ath79_write(struct flash_bank *bank, const uint8_t *buffer,
648 uint32_t offset, uint32_t count)
649 {
650 struct target *target = bank->target;
651 int sector;
652
653 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
654 __func__, offset, count);
655
656 if (target->state != TARGET_HALTED) {
657 LOG_ERROR("Target not halted");
658 return ERROR_TARGET_NOT_HALTED;
659 }
660
661 if (offset + count > bank->size) {
662 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
663 count = bank->size - offset;
664 }
665
666 /* Check sector protection */
667 for (sector = 0; sector < bank->num_sectors; sector++) {
668 /* Start offset in or before this sector? */
669 /* End offset in or behind this sector? */
670 struct flash_sector *bs = &bank->sectors[sector];
671
672 if ((offset < (bs->offset + bs->size)) &&
673 ((offset + count - 1) >= bs->offset) &&
674 bs->is_protected) {
675 LOG_ERROR("Flash sector %d protected", sector);
676 return ERROR_FAIL;
677 }
678 }
679
680 return ath79_write_buffer(bank, buffer, offset, count);
681 }
682
683 static int ath79_read_buffer(struct flash_bank *bank, uint8_t *buffer,
684 uint32_t address, uint32_t len)
685 {
686 uint8_t spi_bytes[] = {
687 SPIFLASH_READ,
688 address >> 16,
689 address >> 8,
690 address,
691 };
692 int retval;
693
694 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
695 __func__, address, len);
696
697 if (address & 0xff) {
698 LOG_ERROR("ath79_read_buffer: unaligned read address: %08x",
699 address);
700 return ERROR_FAIL;
701 }
702
703 LOG_INFO("reading %d bytes from flash @0x%08x", len, address);
704
705 /* bitbang command */
706 ath79_spi_bitbang_prepare(bank);
707 retval = ath79_spi_bitbang_bytes(
708 bank, spi_bytes, sizeof(spi_bytes), ATH79_XFER_PARTIAL);
709 if (retval != ERROR_OK)
710 return retval;
711
712 /* read data */
713 return ath79_spi_bitbang_bytes(
714 bank, buffer, len, ATH79_XFER_FINAL);
715 }
716
717 static int ath79_read(struct flash_bank *bank, uint8_t *buffer,
718 uint32_t offset, uint32_t count)
719 {
720 struct target *target = bank->target;
721
722 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
723 __func__, offset, count);
724
725 if (target->state != TARGET_HALTED) {
726 LOG_ERROR("Target not halted");
727 return ERROR_TARGET_NOT_HALTED;
728 }
729
730 if (offset + count > bank->size) {
731 LOG_WARNING("Reads past end of flash. Extra data discarded.");
732 count = bank->size - offset;
733 }
734
735 return ath79_read_buffer(bank, buffer, offset, count);
736 }
737
738 /* Return ID of flash device */
739 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
740 {
741 struct target *target = bank->target;
742 int retval;
743 uint8_t spi_bytes[] = {SPIFLASH_READ_ID, 0, 0, 0};
744
745 if (target->state != TARGET_HALTED) {
746 LOG_ERROR("Target not halted");
747 return ERROR_TARGET_NOT_HALTED;
748 }
749
750 /* Send SPI command "read ID" */
751 ath79_spi_bitbang_prepare(bank);
752 retval = ath79_spi_bitbang_bytes(
753 bank, spi_bytes, sizeof(spi_bytes), ATH79_XFER_FINAL);
754 if (retval != ERROR_OK)
755 return retval;
756
757 *id = (spi_bytes[1] << 0)
758 | (spi_bytes[2] << 8)
759 | (spi_bytes[3] << 16);
760
761 if (*id == 0xffffff) {
762 LOG_ERROR("No SPI flash found");
763 return ERROR_FAIL;
764 }
765
766 return ERROR_OK;
767 }
768
769 static int ath79_probe(struct flash_bank *bank)
770 {
771 struct target *target = bank->target;
772 struct ath79_flash_bank *ath79_info = bank->driver_priv;
773 struct flash_sector *sectors;
774 uint32_t id = 0; /* silence uninitialized warning */
775 uint32_t pagesize, sectorsize;
776 const struct ath79_target *target_device;
777 int retval;
778
779 if (ath79_info->probed) {
780 free(bank->sectors);
781 free(ath79_info->spi.page_buf);
782 }
783 ath79_info->probed = 0;
784
785 for (target_device = target_devices; target_device->name;
786 ++target_device)
787 if (target_device->tap_idcode == target->tap->idcode)
788 break;
789 if (!target_device->name) {
790 LOG_ERROR("Device ID 0x%" PRIx32 " is not known",
791 target->tap->idcode);
792 return ERROR_FAIL;
793 }
794
795 ath79_info->io_base = target_device->io_base;
796
797 LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
798 target_device->name, bank->base);
799
800 retval = read_flash_id(bank, &id);
801 if (retval != ERROR_OK)
802 return retval;
803
804 ath79_info->dev = NULL;
805 for (const struct flash_device *p = flash_devices; p->name; p++)
806 if (p->device_id == id) {
807 ath79_info->dev = p;
808 break;
809 }
810
811 if (!ath79_info->dev) {
812 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
813 return ERROR_FAIL;
814 }
815
816 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
817 ath79_info->dev->name, ath79_info->dev->device_id);
818
819 /* Set correct size value */
820 bank->size = ath79_info->dev->size_in_bytes;
821 if (bank->size <= (1UL << 16))
822 LOG_WARNING("device needs 2-byte addresses - not implemented");
823 if (bank->size > (1UL << 24))
824 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
825
826 /* if no sectors, treat whole bank as single sector */
827 sectorsize = ath79_info->dev->sectorsize ?
828 ath79_info->dev->sectorsize : ath79_info->dev->size_in_bytes;
829
830 /* create and fill sectors array */
831 bank->num_sectors = ath79_info->dev->size_in_bytes / sectorsize;
832 sectors = calloc(1, sizeof(struct flash_sector) * bank->num_sectors);
833 if (!sectors) {
834 LOG_ERROR("not enough memory");
835 return ERROR_FAIL;
836 }
837
838 /* if no write pagesize, use reasonable default */
839 pagesize = ath79_info->dev->pagesize ? ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
840
841 ath79_info->spi.page_buf = malloc(pagesize);
842 if (!ath79_info->spi.page_buf) {
843 LOG_ERROR("not enough memory");
844 free(sectors);
845 return ERROR_FAIL;
846 }
847
848 for (int sector = 0; sector < bank->num_sectors; sector++) {
849 sectors[sector].offset = sector * sectorsize;
850 sectors[sector].size = sectorsize;
851 sectors[sector].is_erased = 0;
852 sectors[sector].is_protected = 1;
853 }
854
855 bank->sectors = sectors;
856 ath79_info->probed = 1;
857 return ERROR_OK;
858 }
859
860 static int ath79_auto_probe(struct flash_bank *bank)
861 {
862 struct ath79_flash_bank *ath79_info = bank->driver_priv;
863
864 if (ath79_info->probed)
865 return ERROR_OK;
866 return ath79_probe(bank);
867 }
868
869 static int ath79_flash_blank_check(struct flash_bank *bank)
870 {
871 /* Not implemented */
872 return ERROR_OK;
873 }
874
875 static int ath79_protect_check(struct flash_bank *bank)
876 {
877 /* Not implemented */
878 return ERROR_OK;
879 }
880
881 static int get_ath79_info(struct flash_bank *bank, char *buf, int buf_size)
882 {
883 struct ath79_flash_bank *ath79_info = bank->driver_priv;
884
885 if (!ath79_info->probed) {
886 snprintf(buf, buf_size,
887 "\nATH79 flash bank not probed yet\n");
888 return ERROR_OK;
889 }
890
891 snprintf(buf, buf_size, "\nATH79 flash information:\n"
892 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
893 ath79_info->dev->name, ath79_info->dev->device_id);
894
895 return ERROR_OK;
896 }
897
898 const struct flash_driver ath79_flash = {
899 .name = "ath79",
900 .flash_bank_command = ath79_flash_bank_command,
901 .erase = ath79_erase,
902 .protect = ath79_protect,
903 .write = ath79_write,
904 .read = ath79_read,
905 .probe = ath79_probe,
906 .auto_probe = ath79_auto_probe,
907 .erase_check = ath79_flash_blank_check,
908 .protect_check = ath79_protect_check,
909 .info = get_ath79_info,
910 .free_driver_priv = default_flash_free_driver_priv,
911 };