contrib/loaders/flash/armv4_5_cfi_span_16.s

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *   Copyright (C) 2010 Spencer Oliver                                     *
   7  *   spen@spen-soft.co.uk                                                  *
   8  ***************************************************************************/
   9
  10         .text
  11         .arm
  12         .arch armv4
  13
  14         .section .init
  15
  16 /* input parameters - */
  17 /*      R0 = source address */
  18 /*      R1 = destination address */
  19 /*      R2 = number of writes */
  20 /*      R3 = flash write command */
  21 /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
  22 /* output parameters - */
  23 /*      R5 = 0x80 ok 0x00 bad */
  24 /* temp registers - */
  25 /*      R6 = value read from flash to test status */
  26 /*      R7 = holding register */
  27 /* unlock registers - */
  28 /*  R8 = unlock1_addr */
  29 /*  R9 = unlock1_cmd */
  30 /*  R10 = unlock2_addr */
  31 /*  R11 = unlock2_cmd */
  32
  33 code:
  34         ldrh    r5, [r0], #2
  35         strh    r9, [r8]
  36         strh    r11, [r10]
  37         strh    r3, [r8]
  38         strh    r5, [r1]
  39         nop
  40 busy:
  41         ldrh    r6, [r1]
  42         eor             r7, r5, r6
  43         ands    r7, r4, r7
  44         beq             cont                    /* b if DQ7 == Data7 */
  45         ands    r6, r6, r4, lsr #2
  46         beq             busy                    /* b if DQ5 low */
  47         ldrh    r6, [r1]
  48         eor             r7, r5, r6
  49         ands    r7, r4, r7
  50         beq             cont                    /* b if DQ7 == Data7 */
  51         mov             r5, #0                  /* 0x0 - return 0x00, error */
  52         bne             done
  53 cont:
  54         subs    r2, r2, #1              /* 0x1 */
  55         moveq   r5, #128                /* 0x80 */
  56         beq             done
  57         add             r1, r1, #2              /* 0x2 */
  58         b               code
  59 done:
  60         b               done
  61
  62         .end