stm32l: split l0/l1 support no jtag, different HSI settings 05/2405/2
authorKarl Palsson <karlp@tweak.net.au>
Fri, 21 Nov 2014 22:14:57 +0000 (22:14 +0000)
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>
Wed, 3 Dec 2014 09:10:21 +0000 (09:10 +0000)
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup.  It has no endian options, no boundary scan.

Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose.  The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.

Tested on STM32L053 Discovery and STM32L151 Discovery.

Has _not_ been tested with jtag on L1.

Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
tcl/board/stm32l0discovery.cfg
tcl/board/stm32ldiscovery.cfg
tcl/target/stm32l0.cfg [new file with mode: 0644]
tcl/target/stm32l1.cfg [moved from tcl/target/stm32l.cfg with 85% similarity]
tcl/target/stm32l1x_dual_bank.cfg [moved from tcl/target/stm32lx_dual_bank.cfg with 69% similarity]
tcl/target/stm32lx_stlink.cfg

index e1be9a885cdc9f2069056276da30a48b47b6b860..57b8a60027cea87fce50d1ad23a98cc97a398d1e 100644 (file)
@@ -6,7 +6,7 @@ source [find interface/stlink-v2-1.cfg]
 transport select hla_swd
 
 set WORKAREASIZE 0x2000
-source [find target/stm32l.cfg]
+source [find target/stm32l0.cfg]
 
 # use hardware reset, connect under reset
 reset_config srst_only srst_nogate
index fd8c974e4221900eecc5426c487fa84e5a8b9edc..b31a663a409a46f7d78bb71f7ddee0bffbc20832 100644 (file)
@@ -6,7 +6,7 @@ source [find interface/stlink-v2.cfg]
 transport select hla_swd
 
 set WORKAREASIZE 0x4000
-source [find target/stm32l.cfg]
+source [find target/stm32l1.cfg]
 
 # use hardware reset, connect under reset
 reset_config srst_only srst_nogate
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
new file mode 100644 (file)
index 0000000..fc2751e
--- /dev/null
@@ -0,0 +1,73 @@
+#
+# M0+ devices only have SW-DP, but swj-dp code works, just don't
+# set any jtag related features
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l0
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 8kB (max ram on smallest part)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
+adapter_khz 300
+
+adapter_nsrst_delay 100
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    # Arm, m0+, non-multidrop.
+    # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l0_enable_HSI16 {} {
+       # Enable HSI16 as clock source
+       echo "STM32L0: Enabling HSI16"
+
+       # Set HSI16ON in RCC_CR (leave MSI enabled)
+       mww 0x40021000 0x00000101
+
+       # Set HSI16 as SYSCLK (RCC_CFGR)
+       mww 0x4002100c 0x00000001
+
+       # Increase speed
+       adapter_khz 2500
+}
+
+$_TARGETNAME configure -event reset-init {
+       stm32l0_enable_HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+       adapter_khz 300
+}
similarity index 85%
rename from tcl/target/stm32l.cfg
rename to tcl/target/stm32l1.cfg
index 8f6d90550a6bf335f7bf71dac8001f212a778d80..8b83d3f36c402176f10557bf81280027a4481581 100644 (file)
@@ -1,8 +1,7 @@
-# script for stm32l
-
 #
-# stm32 devices support both JTAG and SWD transports.
+# stm32l1 devices support both JTAG and SWD transports.
 #
+
 source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
@@ -42,17 +41,13 @@ if { [info exists CPUTAPID] } {
       # See STM Document RM0038
       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
       set _CPUTAPID 0x4ba00477
-   } {
-      set _CPUTAPID1 0x2ba01477
-      set _CPUTAPID2 0x0bc11477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x2ba01477
    }
 }
 
-if { [using_jtag] } {
-   swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-} else {
-   swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID1 -expected-id $_CPUTAPID2
-}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
@@ -93,13 +88,13 @@ if {![using_hla]} {
 proc stm32l_enable_HSI {} {
        # Enable HSI as clock source
        echo "STM32L: Enabling HSI"
-       
+
        # Set HSION in RCC_CR
        mww 0x40023800 0x00000101
-       
+
        # Set HSI as SYSCLK
        mww 0x40023808 0x00000001
-       
+
        # Increase JTAG speed
        adapter_khz 2000
 }
similarity index 69%
rename from tcl/target/stm32lx_dual_bank.cfg
rename to tcl/target/stm32l1x_dual_bank.cfg
index 8105680f65ac50a6b5ec5ee52a6d90733b304c16..7420b315e0e270d1a3f58c7beb905efbcc02f2d2 100644 (file)
@@ -1,6 +1,6 @@
-source [find target/stm32l.cfg]
+source [find target/stm32l1.cfg]
 
-# The stm32lx 384kb have a dual bank flash.
+# The stm32l1x 384kb have a dual bank flash.
 # Let's add a definition for the second bank here.
 
 # Add the second flash bank.
index 5835348517f7f3c6ccae3546d0ca15108db3aacc..5f694b546fbe866899d3694298d2078a99f2f46e 100644 (file)
@@ -1,2 +1,2 @@
-echo "WARNING: target/stm32lx_stlink.cfg is deprecated, please switch to target/stm32l.cfg"
-source [find target/stm32l.cfg]
+echo "WARNING: target/stm32lx_stlink.cfg is deprecated, please switch to target/stm32l1.cfg"
+source [find target/stm32l1.cfg]

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)