/* target execution control */
int arm11_halt(struct target_s *target)
{
+ int retval = ERROR_OK;
+
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
u32 dscr;
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
- target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
+ if((retval = target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
+ int retval = ERROR_OK;
+
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
while (1)
{
if (!debug_execution)
{
- target->state = TARGET_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
- target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ target->state = TARGET_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
- target->state = TARGET_DEBUG_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+ target->state = TARGET_DEBUG_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
return ERROR_OK;
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
+ int retval = ERROR_OK;
+
FNC_INFO;
LOG_DEBUG("target->state: %s",
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
/** \todo TODO: add a timeout */
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
goto restore;
}
- target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
+ // no debug, otherwise breakpoint is not set
+ if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+ {
+ return retval;
+ }
- target_wait_state(target, TARGET_HALTED, timeout_ms);
if (target->state != TARGET_HALTED)
{
if ((retval=target_halt(target))!=ERROR_OK)
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
+ int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
arm11->jtag_info.chain_pos = target->chain_position;
arm11->jtag_info.scann_size = 5;
- arm_jtag_setup_connection(&arm11->jtag_info);
+ if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
+ {
+ return retval;
+ }
jtag_device_t *device = jtag_get_device(target->chain_position);
int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0xf);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+ if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+ {
+ return retval;
+ }
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 1;
jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
int arm720t_soft_reset_halt(struct target_s *target)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- target_halt(target);
+ if ((retval = target_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
long long then=timeval_ms();
int timeout;
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
} else
{
break;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
return ERROR_OK;
}
- jtag_execute_queue();
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
}
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
+ if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if (verify != arm7_9->arm_bkpt)
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
- target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
+ if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if (verify != arm7_9->thumb_bkpt)
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval = ERROR_OK;
+
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9->wp1_used = 0;
}
- jtag_execute_queue();
+ retval = jtag_execute_queue();
breakpoint->set = 0;
}
else
breakpoint->set = 0;
}
- return ERROR_OK;
+ return retval;
}
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm7_9_unset_breakpoint(target, breakpoint);
+ if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
if (breakpoint->type == BKPT_HARD)
arm7_9->wp_available++;
if (arm7_9->breakpoint_count==0)
{
/* make sure we don't have any dangling breakpoints */
- arm7_9_clear_watchpoints(arm7_9);
+ if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+ {
+ return retval;
+ }
}
return ERROR_OK;
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int rw_mask = 1;
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
watchpoint->set = 1;
arm7_9->wp0_used = 2;
}
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
watchpoint->set = 2;
arm7_9->wp1_used = 2;
}
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (watchpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->wp0_used = 0;
}
else if (watchpoint->set == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->wp1_used = 0;
}
watchpoint->set = 0;
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (watchpoint->set)
{
- arm7_9_unset_watchpoint(target, watchpoint);
+ if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
}
arm7_9->wp_available++;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 *data;
- int i;
+ int i, retval = ERROR_OK;
data = malloc(size * (sizeof(u32)));
- embeddedice_receive(jtag_info, data, size);
+ retval = embeddedice_receive(jtag_info, data, size);
for (i = 0; i < size; i++)
{
free(data);
- return ERROR_OK;
+ return retval;
}
int arm7_9_handle_target_request(void *priv)
{
+ int retval = ERROR_OK;
target_t *target = priv;
if (!target->type->examined)
return ERROR_OK;
{
/* read DCC control register */
embeddedice_read_reg(dcc_control);
- jtag_execute_queue();
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
/* check W bit */
if (buf_get_u32(dcc_control->value, 1, 1) == 1)
{
u32 request;
- embeddedice_receive(jtag_info, &request, 1);
- target_request(target, request);
+ if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_request(target, request)) != ERROR_OK)
+ {
+ return retval;
+ }
}
}
}
}
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
if (target->state == TARGET_DEBUG_RUNNING)
{
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
if (target->state != TARGET_HALTED)
{
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- arm7_9_clear_halt(target);
+ if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
/* if the target is in Thumb state, change to ARM state */
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
}
/* all register content is now invalid */
- armv4_5_invalidate_core_regs(target);
+ if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
+ {
+ return retval;
+ }
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
}
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- arm7_9_clear_halt(target);
+ if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
{
u32 spsr;
arm7_9->read_xpsr(target, &spsr, 1);
- jtag_execute_queue();
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- int err;
+ int err, retval = ERROR_OK;
LOG_DEBUG("-");
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
- arm7_9_unset_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_DEBUG("enable single-step");
arm7_9->enable_single_step(target);
target->debug_reason = DBG_REASON_SINGLESTEP;
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
arm7_9->branch_resume(target);
if (err != ERROR_OK)
{
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
target->state = TARGET_UNKNOWN;
return err;
}
LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
}
}
arm7_9_enable_breakpoints(target);
arm7_9_enable_watchpoints(target);
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
- arm7_9_restart_core(target);
+ if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
+ {
+ return retval;
+ }
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RUNNING;
- target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
target->state = TARGET_DEBUG_RUNNING;
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
LOG_DEBUG("target resumed");
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = NULL;
- int err;
+ int err, retval;
if (target->state != TARGET_HALTED)
{
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
- arm7_9_unset_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
target->debug_reason = DBG_REASON_SINGLESTEP;
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->enable_single_step(target);
return ERROR_FAIL;
}
- target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
err = arm7_9_execute_sys_speed(target);
arm7_9->disable_single_step(target);
target->state = TARGET_UNKNOWN;
} else {
arm7_9_debug_entry(target);
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_DEBUG("target stepped");
}
if (breakpoint)
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
return err;
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
+
}
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
}
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
num_accesses += thisrun_accesses;
}
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
}
num_accesses += thisrun_accesses;
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
+
}
num_accesses += thisrun_accesses;
static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int little=target->endianness==TARGET_LITTLE_ENDIAN;
}
}
- target_halt(target);
+ if((retval = target_halt(target))!= ERROR_OK)
+ {
+ return retval;
+ }
return target_wait_state(target, TARGET_HALTED, 500);
}
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
- target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
+ if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
+ {
+ return retval;
+ }
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
mode = strtoul(args[1], NULL, 0);
value = strtoul(args[2], NULL, 0);
- arm7_9_write_core_reg(target, num, mode, value);
+ return arm7_9_write_core_reg(target, num, mode, value);
- return ERROR_OK;
}
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
- arm_jtag_setup_connection(&arm7_9->jtag_info);
+ if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+ {
+ return retval;
+ }
+
arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
arm7_9->wp_available_max = 2;
arm7_9->sw_breakpoints_added = 0;
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
- armv4_5_init_arch_info(target, armv4_5);
+ if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+ {
+ return retval;
+ }
- target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
+ if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
int arm7tdmi_examine_debug_reason(target_t *target)
{
+ int retval = ERROR_OK;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- arm_jtag_scann(&arm7_9->jtag_info, 0x1);
+ if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, TAP_PD);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
fields[0].in_value = NULL;
fields[0].out_value = &breakpoint;
/* clock the target, reading the databus */
int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
+ int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
if (in)
{
*/
int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
+ int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
if (in)
{
retval = arm7_9_register_commands(cmd_ctx);
- return ERROR_OK;
+ return retval;
}
int arm920t_soft_reset_halt(struct target_s *target)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- target_halt(target);
+ if((retval = target_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
long long then=timeval_ms();
int timeout;
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
} else
{
break;
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
- return ERROR_OK;
+ return retval;
}
int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
+ int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
cp15_ctrl_saved = cp15_ctrl;
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
/* read D RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
d_cache[segment][index].cam = regs[9];
/* read I RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
i_cache[segment][index].cam = regs[9];
int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
+ int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
cp15_ctrl_saved = cp15_ctrl;
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
/* read CP15 test state register */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
/* prepare reading D TLB content
* */
/* read D TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
Dlockdown = regs[1];
for (victim = 0; victim < 64; victim += 8)
/* read D TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
for (i = 0; i < 8; i++)
d_tlb[victim + i].cam = regs[i + 2];
/* read D TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
d_tlb[victim].ram1 = regs[2];
d_tlb[victim].ram2 = regs[3];
/* read I TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
Ilockdown = regs[1];
for (victim = 0; victim < 64; victim += 8)
/* read I TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
for (i = 0; i < 8; i++)
i_tlb[i + victim].cam = regs[i + 2];
/* read I TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
i_tlb[victim].ram1 = regs[2];
i_tlb[victim].ram2 = regs[3];
command_print(cmd_ctx, "couldn't access reg %i", address);
return ERROR_OK;
}
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
command_print(cmd_ctx, "%i: %8.8x", address, value);
}
int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
buf_set_u32(address_buf, 0, 14, address);
jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0xf);
+ if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0xf);
+ if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
int arm926ejs_soft_reset_halt(struct target_s *target)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- target_halt(target);
+ if((retval = target_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
long long then=timeval_ms();
int timeout;
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
} else
{
break;
arm926ejs->armv4_5_mmu.mmu_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
-
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- return ERROR_OK;
+ return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
}
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
- return ERROR_OK;
+ return retval;
}
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
command_print(cmd_ctx, "couldn't access register");
return ERROR_OK;
}
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
}
int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u8 nr_w_buf = 0;
jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0xf);
+ if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0xf);
+ if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
command_print(cmd_ctx, "couldn't access reg %i", address);
return ERROR_OK;
}
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
command_print(cmd_ctx, "%i: %8.8x", address, value);
}
arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
- return ERROR_OK;
+ return retval;
}
int arm9tdmi_examine_debug_reason(target_t *target)
{
+ int retval = ERROR_OK;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- arm_jtag_scann(&arm7_9->jtag_info, 0x1);
+ if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_PD);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
fields[0].in_value = NULL;
fields[0].out_value = databus;
/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
{
+ int retval = ERROR_OK;
scan_field_t fields[3];
u8 out_buf[4];
u8 instr_buf[4];
buf_set_u32(&sysspeed_buf, 2, 1, 1);
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
if (in)
{
/* just read data (instruction and data-out = don't care) */
int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
+ int retval = ERROR_OK;;
scan_field_t fields[3];
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
-
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *in);
*/
int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
+ int retval = ERROR_OK;
scan_field_t fields[3];
jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
-
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
{
+ int retval = ERROR_OK;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* NOP fetched, BX in Execute (1) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
/* fix program counter:
* MOV r0, r15 was the 5th instruction (+8)
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
- return ERROR_OK;
+ return retval;
}
int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
{
+ int retval = ERROR_OK;
if(jtag_info->cur_scan_chain != new_scan_chain)
{
u32 values[1];
values[0]=new_scan_chain;
num_bits[0]=jtag_info->scann_size;
-
- arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL);
- jtag_add_dr_out(jtag_info->chain_pos,
+
+ if((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ jtag_add_dr_out(jtag_info->chain_pos,
1,
num_bits,
values,
jtag_info->cur_scan_chain = new_scan_chain;
}
-
- return ERROR_OK;
+
+ return retval;
}
int arm_jtag_reset_callback(enum jtag_event event, void *priv)
jtag_info->cur_scan_chain = 0;
jtag_info->intest_instr = 0xc;
- jtag_register_event_callback(arm_jtag_reset_callback, jtag_info);
-
- return ERROR_OK;
+ return jtag_register_event_callback(arm_jtag_reset_callback, jtag_info);
}
/* read JTAG buffer into host-endian u32, flipping bit-order */
u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
arm_instruction_t instruction;
int instruction_size;
+ int retval = ERROR_OK;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
u32 opcode;
/* get current instruction, and identify it */
- target_read_u32(target, current_pc, &opcode);
- arm_evaluate_opcode(opcode, current_pc, &instruction);
+ if((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
+ {
+ return retval;
+ }
instruction_size = 4;
/* check condition code (for all instructions) */
{
u16 opcode;
- target_read_u16(target, current_pc, &opcode);
- thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
+ {
+ return retval;
+ }
instruction_size = 2;
/* check condition code (only for branch instructions) */
load_address = Rn;
}
- target_read_u32(target, load_address, &load_value);
+ if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+ {
+ return retval;
+ }
if (dry_run_pc)
{
int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
+ int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5 = target->arch_info;
u32 address;
for (i = 0; i < count; i++)
{
- target_read_u32(target, address, &opcode);
- arm_evaluate_opcode(opcode, address, &cur_instruction);
+ if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+ {
+ return retval;
+ }
command_print(cmd_ctx, "%s", cur_instruction.text);
address += (thumb) ? 2 : 4;
}
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
- target_wait_state(target, TARGET_HALTED, timeout_ms);
+ if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+ {
+ return retval;
+ }
if (target->state != TARGET_HALTED)
{
if ((retval=target_halt(target))!=ERROR_OK)
for (i = 0; i < num_mem_params; i++)
{
- target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+ if((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+ {
+ return retval;
+ }
}
for (i = 0; i < num_reg_params; i++)
exit(-1);
}
- armv4_5_set_core_reg(reg, reg_params[i].value);
+ if((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
+ {
+ return retval;
+ }
}
armv4_5->core_state = armv4_5_algorithm_info->core_state;
return ERROR_TARGET_FAILURE;
}
- target_resume(target, 0, entry_point, 1, 1);
-
+ if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+ {
+ return retval;
+ }
+ int retvaltemp;
retval=run_it(target, exit_point, timeout_ms, arch_info);
breakpoint_remove(target, exit_point);
for (i = 0; i < num_mem_params; i++)
{
if (mem_params[i].direction != PARAM_OUT)
- target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+ if((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+ {
+ retval = retvaltemp;
+ }
}
for (i = 0; i < num_reg_params; i++)
int embeddedice_reg_arch_type = -1;
int embeddedice_get_reg(reg_t *reg);
-int embeddedice_set_reg(reg_t *reg, u32 value);
+void embeddedice_set_reg(reg_t *reg, u32 value);
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
-int embeddedice_write_reg(reg_t *reg, u32 value);
+void embeddedice_write_reg(reg_t *reg, u32 value);
int embeddedice_read_reg(reg_t *reg);
reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
return embeddedice_read_reg_w_check(reg, NULL, NULL);
}
-int embeddedice_set_reg(reg_t *reg, u32 value)
+void embeddedice_set_reg(reg_t *reg, u32 value)
{
- if (embeddedice_write_reg(reg, value) != ERROR_OK)
- {
- LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
- exit(-1);
- }
+ embeddedice_write_reg(reg, value);
buf_set_u32(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->dirty = 0;
- return ERROR_OK;
}
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
return ERROR_OK;
}
-int embeddedice_write_reg(reg_t *reg, u32 value)
+void embeddedice_write_reg(reg_t *reg, u32 value)
{
embeddedice_reg_t *ice_reg = reg->arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
- return ERROR_OK;
}
-int embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(reg_t *reg)
{
- return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+ embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
/* send <size> words of 32 bit to the DCC
extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
extern int embeddedice_setup(target_t *target);
extern int embeddedice_read_reg(reg_t *reg);
-extern int embeddedice_write_reg(reg_t *reg, u32 value);
+extern void embeddedice_write_reg(reg_t *reg, u32 value);
extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
-extern int embeddedice_store_reg(reg_t *reg);
-extern int embeddedice_set_reg(reg_t *reg, u32 value);
+extern void embeddedice_store_reg(reg_t *reg);
+extern void embeddedice_set_reg(reg_t *reg, u32 value);
extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
Code Review / openocd.git / commitdiff