From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Tue, 14 Oct 2008 11:06:30 +0000 (+0000)
Subject: Laurentiu Cocanu - add error handling
X-Git-Tag: v0.1.0~252
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=257d238e618ead82009058efad7e7a7e7102825a

Laurentiu Cocanu - add error handling

git-svn-id: svn://svn.berlios.de/openocd/trunk@1057 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 384b9d064c..49172021c4 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -709,6 +709,8 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
 /* target execution control */
 int arm11_halt(struct target_s *target)
 {
+	int retval = ERROR_OK;
+	
 	FNC_INFO;
 
 	arm11_common_t * arm11 = target->arch_info;
@@ -735,7 +737,10 @@ int arm11_halt(struct target_s *target)
 
 	arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
 
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	u32 dscr;
 
@@ -754,14 +759,19 @@ int arm11_halt(struct target_s *target)
 	target->state		= TARGET_HALTED;
 	target->debug_reason	= arm11_get_DSCR_debug_reason(dscr);
 
-	target_call_event_callbacks(target,
-	old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
+	if((retval = target_call_event_callbacks(target,
+			old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	return ERROR_OK;
 }
 
 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 {
+	int retval = ERROR_OK;
+
 	FNC_INFO;
 
 //	  LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
@@ -833,7 +843,10 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 	arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
 
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	while (1)
 	{
@@ -847,15 +860,21 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 	if (!debug_execution)
 	{
-	target->state		= TARGET_RUNNING;
-	target->debug_reason	= DBG_REASON_NOTHALTED;
-	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+		target->state		= TARGET_RUNNING;
+		target->debug_reason	= DBG_REASON_NOTHALTED;
+		if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 	else
 	{
-	target->state		= TARGET_DEBUG_RUNNING;
-	target->debug_reason	= DBG_REASON_NOTHALTED;
-	target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+		target->state		= TARGET_DEBUG_RUNNING;
+		target->debug_reason	= DBG_REASON_NOTHALTED;
+		if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	return ERROR_OK;
@@ -863,6 +882,8 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 {
+	int retval = ERROR_OK;
+
 	FNC_INFO;
 
 	LOG_DEBUG("target->state: %s",
@@ -937,7 +958,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 
 	arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
 
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	/** \todo TODO: add a timeout */
 
@@ -964,7 +988,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 //	  target->state		= TARGET_HALTED;
 	target->debug_reason	= DBG_REASON_SINGLESTEP;
 
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	return ERROR_OK;
 }
@@ -1411,9 +1438,17 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 		goto restore;
 	}
 
-	target_resume(target, 0, entry_point, 1, 0);  // no debug, otherwise breakpoint is not set
+	// no debug, otherwise breakpoint is not set
+	if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+	{
+		return retval;
+	}
 
-	target_wait_state(target, TARGET_HALTED, timeout_ms);
 	if (target->state != TARGET_HALTED)
 	{
 		if ((retval=target_halt(target))!=ERROR_OK)
@@ -1483,6 +1518,7 @@ restore:
 
 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
 {
+	int retval = ERROR_OK;
 	FNC_INFO;
 
 	NEW(arm11_common_t, arm11, 1);
@@ -1493,7 +1529,10 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp)
 	arm11->jtag_info.chain_pos	= target->chain_position;
 	arm11->jtag_info.scann_size	= 5;
 
-	arm_jtag_setup_connection(&arm11->jtag_info);
+	if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	jtag_device_t *device = jtag_get_device(target->chain_position);
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index ba9d1f6d5c..e95f267683 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -89,6 +89,7 @@ target_type_t arm720t_target =
 
 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -99,8 +100,14 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 	buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 	
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	{
+		return retval;
+	}
+	if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+	{
+		return retval;
+	}
 		
 	fields[0].device = jtag_info->chain_pos;
 	fields[0].num_bits = 1;
@@ -135,7 +142,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 		jtag_add_runtest(0, -1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	if (in)
 		LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
@@ -363,13 +373,17 @@ int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
 
 int arm720t_soft_reset_halt(struct target_s *target)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 	arm720t_common_t *arm720t = arm7tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 	
-	target_halt(target);
+	if ((retval = target_halt(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	long long then=timeval_ms();
 	int timeout;
@@ -378,7 +392,10 @@ int arm720t_soft_reset_halt(struct target_s *target)
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
 			embeddedice_read_reg(dbg_stat);
-			jtag_execute_queue();
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 		} else
 		{
 			break;
@@ -417,7 +434,10 @@ int arm720t_soft_reset_halt(struct target_s *target)
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	return ERROR_OK;
 }
@@ -531,7 +551,11 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 				command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 				return ERROR_OK;
 			}
-			jtag_execute_queue();
+
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 			
 			command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 		}
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 225dd9ecb2..39e469819c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -219,7 +219,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			/* keep the original instruction in target endianness */
 			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
-			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
+			if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
 			if (verify != arm7_9->arm_bkpt)
@@ -234,7 +237,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			/* keep the original instruction in target endianness */
 			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
-			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
+			if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
 			if (verify != arm7_9->thumb_bkpt)
@@ -252,6 +258,8 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
+	int retval = ERROR_OK;
+
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
@@ -273,7 +281,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 			arm7_9->wp1_used = 0;
 		}
-		jtag_execute_queue();
+		retval = jtag_execute_queue();
 		breakpoint->set = 0;
 	}
 	else
@@ -298,7 +306,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		breakpoint->set = 0;
 	}
 
-	return ERROR_OK;
+	return retval;
 }
 
 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
@@ -360,10 +368,14 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-	arm7_9_unset_breakpoint(target, breakpoint);
+	if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	if (breakpoint->type == BKPT_HARD)
 		arm7_9->wp_available++;
@@ -372,7 +384,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	if (arm7_9->breakpoint_count==0)
 	{
 		/* make sure we don't have any dangling breakpoints */
-		arm7_9_clear_watchpoints(arm7_9);
+		if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	return ERROR_OK;
@@ -380,6 +395,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	int rw_mask = 1;
@@ -408,7 +424,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		watchpoint->set = 1;
 		arm7_9->wp0_used = 2;
 	}
@@ -422,7 +441,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		watchpoint->set = 2;
 		arm7_9->wp1_used = 2;
 	}
@@ -437,6 +459,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
@@ -455,13 +478,19 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	if (watchpoint->set == 1)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		arm7_9->wp0_used = 0;
 	}
 	else if (watchpoint->set == 2)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		arm7_9->wp1_used = 0;
 	}
 	watchpoint->set = 0;
@@ -497,12 +526,16 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
 	if (watchpoint->set)
 	{
-		arm7_9_unset_watchpoint(target, watchpoint);
+		if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	arm7_9->wp_available++;
@@ -601,11 +634,11 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	u32 *data;
-	int i;
+	int i, retval = ERROR_OK;
 
 	data = malloc(size * (sizeof(u32)));
 
-	embeddedice_receive(jtag_info, data, size);
+	retval = embeddedice_receive(jtag_info, data, size);
 
 	for (i = 0; i < size; i++)
 	{
@@ -614,11 +647,12 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 
 	free(data);
 
-	return ERROR_OK;
+	return retval;
 }
 
 int arm7_9_handle_target_request(void *priv)
 {
+	int retval = ERROR_OK;
 	target_t *target = priv;
 	if (!target->type->examined)
 		return ERROR_OK;
@@ -635,15 +669,24 @@ int arm7_9_handle_target_request(void *priv)
 	{
 		/* read DCC control register */
 		embeddedice_read_reg(dcc_control);
-		jtag_execute_queue();
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 
 		/* check W bit */
 		if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 		{
 			u32 request;
 
-			embeddedice_receive(jtag_info, &request, 1);
-			target_request(target, request);
+			if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
+			{
+				return retval;
+			}
+			if ((retval = target_request(target, request)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 	}
 
@@ -701,7 +744,10 @@ int arm7_9_poll(target_t *target)
 				}
 			}
 
-			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+			if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 		if (target->state == TARGET_DEBUG_RUNNING)
 		{
@@ -709,7 +755,10 @@ int arm7_9_poll(target_t *target)
 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 				return retval;
 
-			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+			if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 		if (target->state != TARGET_HALTED)
 		{
@@ -919,7 +968,10 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
 
-	arm7_9_clear_halt(target);
+	if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	/* if the target is in Thumb state, change to ARM state */
 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
@@ -932,7 +984,10 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	}
 
 	/* all register content is now invalid */
-	armv4_5_invalidate_core_regs(target);
+	if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
@@ -958,7 +1013,10 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 	}
 
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	return ERROR_OK;
 }
@@ -1044,7 +1102,10 @@ int arm7_9_debug_entry(target_t *target)
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
 
-	arm7_9_clear_halt(target);
+	if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
@@ -1151,7 +1212,10 @@ int arm7_9_debug_entry(target_t *target)
 	{
 		u32 spsr;
 		arm7_9->read_xpsr(target, &spsr, 1);
-		jtag_execute_queue();
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
@@ -1442,7 +1506,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	breakpoint_t *breakpoint = target->breakpoints;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	int err;
+	int err, retval = ERROR_OK;
 
 	LOG_DEBUG("-");
 
@@ -1467,14 +1531,20 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
 		{
 			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
-			arm7_9_unset_breakpoint(target, breakpoint);
+			if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			LOG_DEBUG("enable single-step");
 			arm7_9->enable_single_step(target);
 
 			target->debug_reason = DBG_REASON_SINGLESTEP;
 
-			arm7_9_restore_context(target);
+			if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 				arm7_9->branch_resume(target);
@@ -1497,7 +1567,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 
 			if (err != ERROR_OK)
 			{
-				arm7_9_set_breakpoint(target, breakpoint);
+				if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+				{
+					return retval;
+				}
 				target->state = TARGET_UNKNOWN;
 				return err;
 			}
@@ -1506,7 +1579,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 			LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
 			LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
-			arm7_9_set_breakpoint(target, breakpoint);
+			if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 	}
 
@@ -1514,7 +1590,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 	arm7_9_enable_breakpoints(target);
 	arm7_9_enable_watchpoints(target);
 
-	arm7_9_restore_context(target);
+	if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 	{
@@ -1537,7 +1616,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
 	embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
 
-	arm7_9_restart_core(target);
+	if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 
@@ -1546,12 +1628,18 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		/* registers are now invalid */
 		armv4_5_invalidate_core_regs(target);
 		target->state = TARGET_RUNNING;
-		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+		if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 	else
 	{
 		target->state = TARGET_DEBUG_RUNNING;
-		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+		if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	LOG_DEBUG("target resumed");
@@ -1600,7 +1688,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	breakpoint_t *breakpoint = NULL;
-	int err;
+	int err, retval;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -1615,11 +1703,17 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
-			arm7_9_unset_breakpoint(target, breakpoint);
+			if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+			{
+				return retval;
+			}
 
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 
-	arm7_9_restore_context(target);
+	if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	arm7_9->enable_single_step(target);
 
@@ -1637,7 +1731,10 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		return ERROR_FAIL;
 	}
 
-	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	err = arm7_9_execute_sys_speed(target);
 	arm7_9->disable_single_step(target);
@@ -1650,12 +1747,18 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		target->state = TARGET_UNKNOWN;
 	} else {
 		arm7_9_debug_entry(target);
-		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+		if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+		{
+			return retval;
+		}
 		LOG_DEBUG("target stepped");
 	}
 
 	if (breakpoint)
-		arm7_9_set_breakpoint(target, breakpoint);
+		if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+		{
+			return retval;
+		}
 
 	return err;
 
@@ -1873,9 +1976,14 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 					 * from a sufficiently high clock (32 kHz is usually too slow)
 					 */
 					if (arm7_9->fast_memory_access)
-						arm7_9_execute_fast_sys_speed(target);
+						retval = arm7_9_execute_fast_sys_speed(target);
 					else
-						arm7_9_execute_sys_speed(target);
+						retval = arm7_9_execute_sys_speed(target);
+					if(retval != ERROR_OK)
+					{
+						return retval;
+					}
+
 				}
 
 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
@@ -1906,9 +2014,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 					 * from a sufficiently high clock (32 kHz is usually too slow)
 					 */
 					if (arm7_9->fast_memory_access)
-						arm7_9_execute_fast_sys_speed(target);
+						retval = arm7_9_execute_fast_sys_speed(target);
 					else
-						arm7_9_execute_sys_speed(target);
+						retval = arm7_9_execute_sys_speed(target);
+					if(retval != ERROR_OK)
+					{
+						return retval;
+					}
 				}
 
 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
@@ -2018,9 +2130,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 				 * from a sufficiently high clock (32 kHz is usually too slow)
 				 */
 				if (arm7_9->fast_memory_access)
-					arm7_9_execute_fast_sys_speed(target);
+					retval = arm7_9_execute_fast_sys_speed(target);
 				else
-					arm7_9_execute_sys_speed(target);
+					retval = arm7_9_execute_sys_speed(target);
+				if(retval != ERROR_OK)
+				{
+					return retval;
+				}
 
 				num_accesses += thisrun_accesses;
 			}
@@ -2050,9 +2166,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					 * from a sufficiently high clock (32 kHz is usually too slow)
 					 */
 					if (arm7_9->fast_memory_access)
-						arm7_9_execute_fast_sys_speed(target);
+						retval = arm7_9_execute_fast_sys_speed(target);
 					else
-						arm7_9_execute_sys_speed(target);
+						retval = arm7_9_execute_sys_speed(target);
+					if(retval != ERROR_OK)
+					{
+						return retval;
+					}
 				}
 
 				num_accesses += thisrun_accesses;
@@ -2081,9 +2201,14 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					 * from a sufficiently high clock (32 kHz is usually too slow)
 					 */
 					if (arm7_9->fast_memory_access)
-						arm7_9_execute_fast_sys_speed(target);
+						retval = arm7_9_execute_fast_sys_speed(target);
 					else
-						arm7_9_execute_sys_speed(target);
+						retval = arm7_9_execute_sys_speed(target);
+					if(retval != ERROR_OK)
+					{
+						return retval;
+					}
+
 				}
 
 				num_accesses += thisrun_accesses;
@@ -2130,6 +2255,7 @@ static u8 *dcc_buffer;
 
 static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	int little=target->endianness==TARGET_LITTLE_ENDIAN;
@@ -2161,7 +2287,10 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
 		}
 	}
 
-	target_halt(target);
+	if((retval = target_halt(target))!= ERROR_OK)
+	{
+		return retval;
+	}
 	return target_wait_state(target, TARGET_HALTED, 500);
 }
 
@@ -2348,7 +2477,10 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
 
 	/* convert flash writing code into a buffer in target endianness */
 	for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
-		target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
+		if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
+		{
+			return retval;
+		}
 
 	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
@@ -2528,9 +2660,8 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
 	mode = strtoul(args[1], NULL, 0);
 	value = strtoul(args[2], NULL, 0);
 
-	arm7_9_write_core_reg(target, num, mode, value);
+	return arm7_9_write_core_reg(target, num, mode, value);
 
-	return ERROR_OK;
 }
 
 
@@ -2635,11 +2766,16 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 
 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
 
 	arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-	arm_jtag_setup_connection(&arm7_9->jtag_info);
+	if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+	{
+		return retval;
+	}
+
 	arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
 	arm7_9->wp_available_max = 2;
 	arm7_9->sw_breakpoints_added = 0;
@@ -2668,9 +2804,15 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
 
-	armv4_5_init_arch_info(target, armv4_5);
+	if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+	{
+		return retval;
+	}
 
-	target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
+	if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 99fa9bc43b..4528a83f56 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -97,6 +97,7 @@ target_type_t arm7tdmi_target =
 
 int arm7tdmi_examine_debug_reason(target_t *target)
 {
+	int retval = ERROR_OK;
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -131,11 +132,17 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 		fields[1].in_handler = NULL;
 		fields[1].in_handler_priv = NULL;
 		
-		arm_jtag_scann(&arm7_9->jtag_info, 0x1);
+		if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		{
+			return retval;
+		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
 		jtag_add_dr_scan(2, fields, TAP_PD);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		fields[0].in_value = NULL;
 		fields[0].out_value = &breakpoint;
@@ -182,10 +189,14 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr
 /* clock the target, reading the databus */
 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 {
+	int retval = ERROR_OK;
 	scan_field_t fields[2];
 
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0x1);
+	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 	
 	fields[0].device = jtag_info->chain_pos;
@@ -214,7 +225,10 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 			
 		if (in)
 		{
@@ -236,10 +250,14 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
  */ 
 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 {
+	int retval = ERROR_OK;
 	scan_field_t fields[2];
 
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0x1);
+	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 	
 	fields[0].device = jtag_info->chain_pos;
@@ -279,7 +297,10 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 			
 		if (in)
 		{
@@ -851,6 +872,6 @@ int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 	
 	retval = arm7_9_register_commands(cmd_ctx);
 	
-	return ERROR_OK;
+	return retval;
 
 }
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 5b4c175fdd..b45d0f613f 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -625,13 +625,17 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
 
 int arm920t_soft_reset_halt(struct target_s *target)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 	arm920t_common_t *arm920t = arm9tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 	
-	target_halt(target);
+	if((retval = target_halt(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	long long then=timeval_ms();
 	int timeout;
@@ -640,7 +644,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
 			embeddedice_read_reg(dbg_stat);
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 		} else
 		{
 			break;
@@ -680,7 +687,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	return ERROR_OK;
 }
@@ -770,11 +780,12 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx)
 	register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
 	register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 
-	return ERROR_OK;
+	return retval;
 }
 
 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -816,7 +827,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 	
 	/* disable MMU and Caches */
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	cp15_ctrl_saved = cp15_ctrl;
 	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
@@ -876,7 +890,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 			/* read D RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			d_cache[segment][index].cam = regs[9];
 			
@@ -959,7 +976,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 			/* read I RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 
 			i_cache[segment][index].cam = regs[9];
 			
@@ -1019,6 +1039,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -1060,14 +1081,20 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 	
 	/* disable MMU and Caches */
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	cp15_ctrl_saved = cp15_ctrl;
 	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 
 	/* read CP15 test state register */ 
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 
 	/* prepare reading D TLB content 
 	 * */
@@ -1085,7 +1112,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 	
 	/* read D TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	Dlockdown = regs[1];
 	
 	for (victim = 0; victim < 64; victim += 8)
@@ -1111,7 +1141,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 		
 		/* read D TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		for (i = 0; i < 8; i++)
 			d_tlb[victim + i].cam = regs[i + 2]; 
@@ -1143,7 +1176,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 		
 		/* read D TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 
 		d_tlb[victim].ram1 = regs[2]; 
 		d_tlb[victim].ram2 = regs[3]; 
@@ -1172,7 +1208,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 	
 	/* read I TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	Ilockdown = regs[1];
 	
 	for (victim = 0; victim < 64; victim += 8)
@@ -1198,7 +1237,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 		
 		/* read I TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		for (i = 0; i < 8; i++)
 			i_tlb[i + victim].cam = regs[i + 2]; 
@@ -1230,7 +1272,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 		
 		/* read I TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 
 		i_tlb[victim].ram1 = regs[2]; 
 		i_tlb[victim].ram2 = regs[3]; 
@@ -1317,7 +1362,10 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 				command_print(cmd_ctx, "couldn't access reg %i", address);
 				return ERROR_OK;
 			}
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 			
 			command_print(cmd_ctx, "%i: %8.8x", address, value);
 		}
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 110adee040..9cfdcdd5a7 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -120,6 +120,7 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 
 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -132,7 +133,10 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	buf_set_u32(address_buf, 0, 14, address);
 	
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_scann(jtag_info, 0xf);
+	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].device = jtag_info->chain_pos;
@@ -187,7 +191,10 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 		access = 0;
 		nr_w_buf = 0;
 		jtag_add_dr_scan(4, fields, -1);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 	} while (buf_get_u32(&access, 0, 1) != 1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -201,6 +208,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 
 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -215,7 +223,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	buf_set_u32(value_buf, 0, 32, value);
 	
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_scann(jtag_info, 0xf);
+	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].device = jtag_info->chain_pos;
@@ -266,7 +277,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 		access = 0;
 		nr_w_buf = 0;
 		jtag_add_dr_scan(4, fields, -1);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 	} while (buf_get_u32(&access, 0, 1) != 1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -575,13 +589,17 @@ int arm926ejs_arch_state(struct target_s *target)
 
 int arm926ejs_soft_reset_halt(struct target_s *target)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 	arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 	
-	target_halt(target);
+	if((retval = target_halt(target)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	long long then=timeval_ms();
 	int timeout;
@@ -590,7 +608,10 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
 			embeddedice_read_reg(dbg_stat);
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 		}  else
 		{
 			break;
@@ -629,10 +650,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
-
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 	
-	return ERROR_OK;
+	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
 }
 
 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -749,7 +769,7 @@ int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 	register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 	register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 
-	return ERROR_OK;
+	return retval;
 }
 
 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
@@ -796,7 +816,10 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
 			command_print(cmd_ctx, "couldn't access register");
 			return ERROR_OK;
 		}
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 	}
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index b5b6825cfe..a441acbf72 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -170,6 +170,7 @@ int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
 
 int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -178,7 +179,10 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 	u8 nr_w_buf = 0;
 	
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_scann(jtag_info, 0xf);
+	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].device = jtag_info->chain_pos;
@@ -219,7 +223,10 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 	jtag_add_dr_scan(3, fields, -1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 #endif
 
@@ -228,6 +235,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 
 int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
 {
+	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -239,7 +247,10 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
 	buf_set_u32(value_buf, 0, 32, value);
 	
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_scann(jtag_info, 0xf);
+	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	{
+		return retval;
+	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].device = jtag_info->chain_pos;
@@ -318,7 +329,10 @@ int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 				command_print(cmd_ctx, "couldn't access reg %i", address);
 				return ERROR_OK;
 			}
-			jtag_execute_queue();
+			if((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
 			
 			command_print(cmd_ctx, "%i: %8.8x", address, value);
 		}
@@ -346,5 +360,5 @@ int arm966e_register_commands(struct command_context_s *cmd_ctx)
 	arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
 	register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 	
-	return ERROR_OK;
+	return retval;
 }
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 0937c2abd5..5691bb76c9 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -108,6 +108,7 @@ arm9tdmi_vector_t arm9tdmi_vectors[] =
 
 int arm9tdmi_examine_debug_reason(target_t *target)
 {
+	int retval = ERROR_OK;
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -153,11 +154,17 @@ int arm9tdmi_examine_debug_reason(target_t *target)
 		fields[2].in_handler = NULL;
 		fields[2].in_handler_priv = NULL;
 		
-		arm_jtag_scann(&arm7_9->jtag_info, 0x1);
+		if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		{
+			return retval;
+		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
 		jtag_add_dr_scan(3, fields, TAP_PD);
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		fields[0].in_value = NULL;
 		fields[0].out_value = databus;
@@ -183,6 +190,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 {
+	int retval = ERROR_OK;
 	scan_field_t fields[3];
 	u8 out_buf[4];
 	u8 instr_buf[4];
@@ -197,7 +205,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 		buf_set_u32(&sysspeed_buf, 2, 1, 1);
 	
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0x1);
+	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 		
@@ -245,7 +256,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 	
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		jtag_execute_queue();
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		if (in)
 		{
@@ -262,10 +276,14 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 /* just read data (instruction and data-out = don't care) */
 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 {
+	int retval = ERROR_OK;;
 	scan_field_t fields[3];
 
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0x1);
+	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 		
@@ -305,8 +323,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		jtag_execute_queue();
-			
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
+		
 		if (in)
 		{
 			LOG_DEBUG("in: 0x%8.8x", *in);
@@ -327,10 +348,14 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
  */
 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 {
+	int retval = ERROR_OK;
 	scan_field_t fields[3];
 	
 	jtag_add_end_state(TAP_PD);
-	arm_jtag_scann(jtag_info, 0x1);
+	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 		
@@ -381,8 +406,11 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		jtag_execute_queue();
-			
+		if((retval = jtag_execute_queue()) != ERROR_OK)
+		{
+			return retval;
+		}
+		
 		if (in)
 		{
 			LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
@@ -399,6 +427,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 
 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 {
+	int retval = ERROR_OK;
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -439,7 +468,10 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 	/* NOP fetched, BX in Execute (1) */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 	
-	jtag_execute_queue();
+	if((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
 	
 	/* fix program counter:
 	 * MOV r0, r15 was the 5th instruction (+8)
@@ -1035,7 +1067,7 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
 	register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
 	
 	
-	return ERROR_OK;
+	return retval;
 
 }
 
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 1e2683c186..9452c2b98c 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -63,6 +63,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr,  in_handler_t handl
 
 int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
 {
+	int retval = ERROR_OK;
 	if(jtag_info->cur_scan_chain != new_scan_chain)
 	{
 		u32 values[1];
@@ -70,9 +71,13 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
 		
 		values[0]=new_scan_chain;
 		num_bits[0]=jtag_info->scann_size;
-		
-		arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL);
-		jtag_add_dr_out(jtag_info->chain_pos, 
+
+		if((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL)) != ERROR_OK)
+		{
+			return retval;
+		}
+
+		jtag_add_dr_out(jtag_info->chain_pos,
 				1,
 				num_bits,
 				values,
@@ -80,8 +85,8 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
 		
 		jtag_info->cur_scan_chain = new_scan_chain;
 	}
-	
-	return ERROR_OK;
+
+	return retval;
 }
 
 int arm_jtag_reset_callback(enum jtag_event event, void *priv)
@@ -102,9 +107,7 @@ int arm_jtag_setup_connection(arm_jtag_t *jtag_info)
 	jtag_info->cur_scan_chain = 0;
 	jtag_info->intest_instr = 0xc;
 
-	jtag_register_event_callback(arm_jtag_reset_callback, jtag_info);
-	
-	return ERROR_OK;
+	return jtag_register_event_callback(arm_jtag_reset_callback, jtag_info);
 }
 
 /* read JTAG buffer into host-endian u32, flipping bit-order */
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 40ca35671d..07e180164a 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -272,14 +272,21 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 	u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 	arm_instruction_t instruction;
 	int instruction_size;
+	int retval = ERROR_OK;
 	
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 	{
 		u32 opcode;
 		
 		/* get current instruction, and identify it */
-		target_read_u32(target, current_pc, &opcode);
-		arm_evaluate_opcode(opcode, current_pc, &instruction);
+		if((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
+		{
+			return retval;
+		}
+		if((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
+		{
+			return retval;
+		}
 		instruction_size = 4;
 		
 		/* check condition code (for all instructions) */
@@ -301,8 +308,14 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 	{
 		u16 opcode;
 		
-		target_read_u16(target, current_pc, &opcode);
-		thumb_evaluate_opcode(opcode, current_pc, &instruction);
+		if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
+		{
+			return retval;
+		}
+		if((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
+		{
+			return retval;
+			}
 		instruction_size = 2;
 		
 		/* check condition code (only for branch instructions) */
@@ -520,7 +533,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 			 load_address = Rn;
 		}
 		
-		target_read_u32(target, load_address, &load_value);
+		if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+		{
+			return retval;
+		}
 		
 		if (dry_run_pc)
 		{
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 93dfa8ad34..c4637aee40 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -397,6 +397,7 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c
 
 int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	u32 address;
@@ -427,8 +428,14 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 
 	for (i = 0; i < count; i++)
 	{
-		target_read_u32(target, address, &opcode);
-		arm_evaluate_opcode(opcode, address, &cur_instruction);
+		if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+		{
+			return retval;
+		}
+		if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+		{
+			return retval;
+		}
 		command_print(cmd_ctx, "%s", cur_instruction.text);
 		address += (thumb) ? 2 : 4;
 	}
@@ -482,7 +489,10 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 
-	target_wait_state(target, TARGET_HALTED, timeout_ms);
+	if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+	{
+		return retval;
+	}
 	if (target->state != TARGET_HALTED)
 	{
 		if ((retval=target_halt(target))!=ERROR_OK)
@@ -541,7 +551,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
 	for (i = 0; i < num_mem_params; i++)
 	{
-		target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+		if((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	for (i = 0; i < num_reg_params; i++)
@@ -559,7 +572,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 			exit(-1);
 		}
 
-		armv4_5_set_core_reg(reg, reg_params[i].value);
+		if((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
+		{
+			return retval;
+		}
 	}
 
 	armv4_5->core_state = armv4_5_algorithm_info->core_state;
@@ -587,8 +603,11 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 		return ERROR_TARGET_FAILURE;
 	}
 
-	target_resume(target, 0, entry_point, 1, 1);
-
+	if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+	{
+		return retval;
+	}
+	int retvaltemp;
 	retval=run_it(target, exit_point, timeout_ms, arch_info);
 
 	breakpoint_remove(target, exit_point);
@@ -596,7 +615,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 	for (i = 0; i < num_mem_params; i++)
 	{
 		if (mem_params[i].direction != PARAM_OUT)
-			target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+			if((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+			{
+					retval = retvaltemp;
+			}
 	}
 
 	for (i = 0; i < num_reg_params; i++)
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 883254fc64..7da32fa807 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -86,10 +86,10 @@ char* embeddedice_reg_list[] =
 int embeddedice_reg_arch_type = -1;
 
 int embeddedice_get_reg(reg_t *reg);
-int embeddedice_set_reg(reg_t *reg, u32 value);
+void embeddedice_set_reg(reg_t *reg, u32 value);
 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
 
-int embeddedice_write_reg(reg_t *reg, u32 value);
+void embeddedice_write_reg(reg_t *reg, u32 value);
 int embeddedice_read_reg(reg_t *reg);
 
 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
@@ -369,19 +369,14 @@ int embeddedice_read_reg(reg_t *reg)
 	return embeddedice_read_reg_w_check(reg, NULL, NULL);
 }
 
-int embeddedice_set_reg(reg_t *reg, u32 value)
+void embeddedice_set_reg(reg_t *reg, u32 value)
 {
-	if (embeddedice_write_reg(reg, value) != ERROR_OK)
-	{
-		LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
-		exit(-1);
-	}
+	embeddedice_write_reg(reg, value);
 
 	buf_set_u32(reg->value, 0, reg->size, value);
 	reg->valid = 1;
 	reg->dirty = 0;
 
-	return ERROR_OK;
 }
 
 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
@@ -396,7 +391,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 	return ERROR_OK;
 }
 
-int embeddedice_write_reg(reg_t *reg, u32 value)
+void embeddedice_write_reg(reg_t *reg, u32 value)
 {
 	embeddedice_reg_t *ice_reg = reg->arch_info;
 
@@ -410,12 +405,11 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
 	u8 reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
 
-	return ERROR_OK;
 }
 
-int embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(reg_t *reg)
 {
-	return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+	embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 }
 
 /* send <size> words of 32 bit to the DCC
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index aeb78a7488..92aee2b330 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -99,10 +99,10 @@ typedef struct embeddedice_reg_s
 extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
 extern int embeddedice_setup(target_t *target);
 extern int embeddedice_read_reg(reg_t *reg);
-extern int embeddedice_write_reg(reg_t *reg, u32 value);
+extern void embeddedice_write_reg(reg_t *reg, u32 value);
 extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
-extern int embeddedice_store_reg(reg_t *reg);
-extern int embeddedice_set_reg(reg_t *reg, u32 value);
+extern void embeddedice_store_reg(reg_t *reg);
+extern void embeddedice_set_reg(reg_t *reg, u32 value);
 extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
 extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
 extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);