jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / tcl / target / renesas_rcar_gen3.cfg

diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 334d25568f2a2a0b0708babe08e82446bf82d773..8dc0e7a0ddc695a21949ce1f5500c9b87f97ab6d 100644 (file)
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Renesas R-Car Generation 3 SOCs
 # - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
 # - Each SOC can boot through any of the, up to 3, core types that it has
@@ -154,15 +156,20 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
        }
 }
 
-proc setup_cr7 {core_name dbgbase ctibase num boot} {
+proc setup_crx {core_name dbgbase ctibase num boot} {
        global _CHIPNAME
        global _DAPNAME
        for { set _core 0 } { $_core < $num } { incr _core } {
                set _TARGETNAME $_CHIPNAME.$core_name
                set _CTINAME $_TARGETNAME.cti
                cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
-               set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
-                       -ap-num 1 -dbgbase $dbgbase"
+               if { $core_name == "r52" } {
+                       set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \
+                               -ap-num 1 -dbgbase $dbgbase -cti $_CTINAME"
+               } else {
+                       set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
+                               -ap-num 1 -dbgbase $dbgbase"
+               }
                if { $boot == 1 } {
                        set _targets "$_TARGETNAME"
                } else {
@@ -175,20 +182,20 @@ proc setup_cr7 {core_name dbgbase ctibase num boot} {
 # Organize target list based on the boot core
 if { [string equal $_boot_core CA76] } {
        setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
-       setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
+       setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
 } elseif { [string equal $_boot_core CA57] } {
        setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
        setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
-       setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+       setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
 } elseif { [string equal $_boot_core CA53] } {
        setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
        setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
-       setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+       setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
 } elseif { [string equal $_boot_core CR52] } {
-       setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
+       setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
        setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
 } else {
-       setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1
+       setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1
        setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
        setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 }