target/stm32: make APCSW cacheable

[openocd.git] / tcl / target / mdr32f9q2i.cfg

diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 8e8262d7611e531ced1ce9ad1d574c5363f3d742..67481024c56e4a2839fefd14278941b5e0b3e6d6 100644 (file)
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -26,12 +26,18 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   set _CPUTAPID 0x4ba00477
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
 }
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -46,10 +52,12 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-if {$using_jtag} {
+if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}