target/stm32: make APCSW cacheable

[openocd.git] / tcl / target / lpc2900.cfg

diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index fa5bd5bb78ef4bc5e7be9f24f4ef91742f367bc1..53677873abd8785187f1b4fd1c918dd5ea8af793 100644 (file)
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -1,25 +1,25 @@
 
 if { [info exists CHIPNAME] } {
-    set  _CHIPNAME $CHIPNAME
+    set _CHIPNAME $CHIPNAME
 } else {
-    set  _CHIPNAME lpc2900
+    set _CHIPNAME lpc2900
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
     set _CPUTAPID $CPUTAPID
 } else {
     set _CPUTAPID 0x0596802B
 }
 
-if { [info exists HAS_ETB ] } {
+if { [info exists HAS_ETB] } {
 } else {
     # Set default (no ETB).
     # Show a warning, because this should have been configured explicitely.
     set HAS_ETB 0
-    # TODO   warning?
+    # TODO: warning?
 }
 
-if { [info exists ETBTAPID ] } {
+if { [info exists ETBTAPID] } {
     set _ETBTAPID $ETBTAPID
 } else {
     set _ETBTAPID 0x1B900F0F
@@ -29,7 +29,7 @@ if { [info exists ETBTAPID ] } {
 reset_config trst_and_srst separate
 
 # Define the _TARGETNAME
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 
 # Include the ETB tap controller if asked for.
 # Has to be done manually for newer devices (not an "old" LPC2917/2919).
@@ -42,7 +42,7 @@ if { $HAS_ETB == 1 } {
     jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
     # Create the ".cpu" target
-    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
 
     # Configure ETM and ETB
     etm config $_TARGETNAME 8 normal full etb
@@ -53,13 +53,14 @@ if { $HAS_ETB == 1 } {
     jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
     # Create the ".cpu" target
-    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
 }
 
 arm7_9 dbgrq enable
 arm7_9 dcc_downloads enable
 
 # Flash bank configuration:
-# Flash:   flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
+# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
 # Flash base address, total flash size, and number of sectors are all configured automatically.
-flash bank lpc2900         0 0 0 0 $_TARGETNAME $FLASH_CLOCK
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK