ipdbg: fix double free of virtual-ir data

[openocd.git] / tcl / target / lpc1xxx.cfg

diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 226425d41f3cf1225d7f496cdc2ea87619fa17b1..70d26d2673900b06c6d5eef8e55b4542103e9e42 100644 (file)
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
 #
 # !!!!!!
@@ -56,7 +58,7 @@ if { [info exists CPUTAPID] } {
        # Allow user override
        set _CPUTAPID $CPUTAPID
 } else {
-       # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
+       # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
        if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
                set _CPUTAPID 0x0bb11477
        } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
@@ -75,9 +77,10 @@ if { [info exists WORKAREASIZE] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
 # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
@@ -98,10 +101,14 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
 # (same cmd51 destination boundary alignment, and all three support 256 byte
 # transfers).
 #
-# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry]
+set _IAP_ENTRY 0
+if { [info exists IAP_ENTRY] } {
+       set _IAP_ENTRY $IAP_ENTRY
+}
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
-       auto $_CCLK calc_checksum
+       auto $_CCLK calc_checksum $_IAP_ENTRY
 
 if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
        # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
@@ -140,18 +147,18 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
 
 # delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
 if {[using_jtag]} {
  jtag_ntrst_delay 200
 }
 
-# LPC8xx (Cortex M0+ core) support SYSRESETREQ
-# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
-# LPC40xx (Cortex M4F core) support SYSRESETREQ
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
 if {![using_hla]} {
     # if srst is not fitted use SYSRESETREQ to
     # perform a soft reset