target/stm32: make APCSW cacheable

[openocd.git] / tcl / target / feroceon.cfg

diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg
index 552831a8448e53ce915ef75c1a2a12ee59f86f9f..389576e55c7e0fd058cf0986c1c390aad45043f3 100644 (file)
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -2,29 +2,30 @@
 # Target:    Marvell Feroceon CPU core
 ######################################
 
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
-   set  _CHIPNAME feroceon
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME feroceon
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
-   set  _ENDIAN little
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x20a023d3
 }
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200