jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / tcl / board / pxa255_sst.cfg

diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 76ae4c93bbe8436d22e240b605b7f56939e299c2..8d00dfe6a432a6e2a3c1ed470ba396f8971d2944 100644 (file)
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -1,7 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # A PXA255 test board with SST 39LF400A flash
 #
 # At reset the memory map is as follows. Note that
-# the memory map changes later on as the application 
+# the memory map changes later on as the application
 # starts...
 #
 # RAM at 0x4000000
@@ -10,81 +12,82 @@
 source [find target/pxa255.cfg]
 
 # Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
-flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
 
 proc pxa255_sst_init {} {
-       xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
+       xscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access
        #
        # setup GPIO
        #
-       mww    0x40E00018  0x00008000  #CPSR0
+       mww    0x40E00018  0x00008000  ;#CPSR0
        sleep   20
-       mww    0x40E0001C  0x00000002  #GPSR1
+       mww    0x40E0001C  0x00000002  ;#GPSR1
        sleep   20
-       mww    0x40E00020  0x00000008  #GPSR2
+       mww    0x40E00020  0x00000008  ;#GPSR2
        sleep   20
-       mww    0x40E0000C  0x00008000  #GPDR0
+       mww    0x40E0000C  0x00008000  ;#GPDR0
        sleep   20
-       mww    0x40E00054  0x80000000  #GAFR0_L
+       mww    0x40E00054  0x80000000  ;#GAFR0_L
        sleep   20
-       mww    0x40E00058  0x00188010  #GAFR0_H
+       mww    0x40E00058  0x00188010  ;#GAFR0_H
        sleep   20
-       mww    0x40E0005C  0x60908018  #GAFR1_L
+       mww    0x40E0005C  0x60908018  ;#GAFR1_L
        sleep   20
-       mww    0x40E0000C  0x0280E000  #GPDR0
+       mww    0x40E0000C  0x0280E000  ;#GPDR0
        sleep   20
-       mww    0x40E00010  0x821C88B2  #GPDR1
+       mww    0x40E00010  0x821C88B2  ;#GPDR1
        sleep   20
-       mww    0x40E00014  0x000F03DB  #GPDR2
+       mww    0x40E00014  0x000F03DB  ;#GPDR2
        sleep   20
-       mww    0x40E00000  0x000F03DB  #GPLR0
+       mww    0x40E00000  0x000F03DB  ;#GPLR0
        sleep   20
 
 
-       mww    0x40F00004  0x00000020  #PSSR
+       mww    0x40F00004  0x00000020  ;#PSSR
        sleep   20
 
        #
        # setup memory controller
        #
-       mww    0x48000008  0x01111998  #MSC0
+       mww    0x48000008  0x01111998  ;#MSC0
        sleep   20
-       mww    0x48000010  0x00047ff0  #MSC2
+       mww    0x48000010  0x00047ff0  ;#MSC2
        sleep   20
-       mww    0x48000014  0x00000000  #MECR
+       mww    0x48000014  0x00000000  ;#MECR
        sleep   20
-       mww    0x48000028  0x00010504  #MCMEM0
+       mww    0x48000028  0x00010504  ;#MCMEM0
        sleep   20
-       mww    0x4800002C  0x00010504  #MCMEM1
+       mww    0x4800002C  0x00010504  ;#MCMEM1
        sleep   20
-       mww    0x48000030  0x00010504  #MCATT0
+       mww    0x48000030  0x00010504  ;#MCATT0
        sleep   20
-       mww    0x48000034  0x00010504  #MCATT1
+       mww    0x48000034  0x00010504  ;#MCATT1
        sleep   20
-       mww    0x48000038  0x00004715  #MCIO0
+       mww    0x48000038  0x00004715  ;#MCIO0
        sleep   20
-       mww    0x4800003C  0x00004715  #MCIO1
+       mww    0x4800003C  0x00004715  ;#MCIO1
        sleep   20
        #
-       mww    0x48000004  0x03CA4018  #MDREF
+       mww    0x48000004  0x03CA4018  ;#MDREF
        sleep   20
-       mww    0x48000004  0x004B4018  #MDREF
+       mww    0x48000004  0x004B4018  ;#MDREF
        sleep   20
-       mww    0x48000004  0x000B4018  #MDREF
+       mww    0x48000004  0x000B4018  ;#MDREF
        sleep   20
-       mww    0x48000004  0x000BC018  #MDREF
+       mww    0x48000004  0x000BC018  ;#MDREF
        sleep   20
-       mww    0x48000000  0x00001AC8  #MDCNFG
+       mww    0x48000000  0x00001AC8  ;#MDCNFG
        sleep   20
 
        sleep   20
 
-       mww    0x48000000  0x00001AC9  #MDCNFG
+       mww    0x48000000  0x00001AC9  ;#MDCNFG
        sleep   20
-       mww    0x48000040  0x00000000  #MDMRS
+       mww    0x48000040  0x00000000  ;#MDMRS
        sleep   20
 }
 
@@ -92,7 +95,7 @@ $_TARGETNAME configure -event reset-init {pxa255_sst_init}
 
 reset_config trst_and_srst
 
-jtag_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
-#xscale debug_handler 0  0xFFFF0800      # debug handler base address
+#xscale debug_handler 0  0xFFFF0800      ;# debug handler base address