jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / tcl / board / imx53loco.cfg

diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index e1bc44da3b3d4348c16aba6c6bc28815b67a7155..fcc2f4dda0f0dbb99b39102c7a67d89155d90844 100644 (file)
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ##################################################################################
 # Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
 # Kiwigrid GmbH                                                                  #
@@ -19,7 +21,7 @@ adapter speed 3000
 jtag_rclk 1000
 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
-#jtag_nsrst_delay 200
+#adapter srst delay 200
 #jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event "reset-assert" {
@@ -70,7 +72,7 @@ proc init_l2cc { } {
        set tR [arm mrc 15 0 1 0 1]
        ; #bic r0, r0, #0x2
        ; #mcr 15, 0, r0, c1, c0, 1
-       arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
+       arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
 
        ; #/* reconfigure L2 cache aux control reg */
        ; #mov r0, #0xC0                   /* tag RAM */
@@ -140,7 +142,7 @@ proc init_clock { } {
        mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 
        ; # change uart clk parent to pll2
-       mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
+       mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
 
        ; # make sure change is effective
        while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@ -158,7 +160,7 @@ proc init_clock { } {
        mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 
        ; # make uart div=6
-       mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
+       mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
 
        ; # Restore the default values in the Gate registers
        mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@ -244,7 +246,7 @@ proc setup_pll { PLL_ADDR CLK } {
        mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 
        mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
-       while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
+       while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
 }