+#define MIPS32_ISA_DRET 0x4200001Fu
+/* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
+#define MIPS32_ISA_SDBBP 0x7000003Fu
+#define MIPS16_ISA_SDBBP 0xE801u
+
+/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
+#define MMIPS32_POOL32A 0x00u
+#define MMIPS32_POOL32F 0x15u
+#define MMIPS32_POOL32FXF 0x3Bu
+#define MMIPS32_POOL32AXF 0x3Cu
+#define MMIPS32_POOL32B 0x08u
+#define MMIPS32_POOL32I 0x10u
+#define MMIPS32_OP_ADDI 0x04u
+#define MMIPS32_OP_ADDIU 0x0Cu
+#define MMIPS32_OP_ADDU 0x150u
+#define MMIPS32_OP_AND 0x250u
+#define MMIPS32_OP_ANDI 0x34u
+#define MMIPS32_OP_BEQ 0x25u
+#define MMIPS32_OP_BGTZ 0x06u
+#define MMIPS32_OP_BNE 0x2Du
+#define MMIPS32_OP_CACHE 0x06u
+#define MMIPS32_OP_CFC1 0x40u
+#define MMIPS32_OP_J 0x35u
+#define MMIPS32_OP_JALR 0x03Cu
+#define MMIPS32_OP_JALRHB 0x07Cu
+#define MMIPS32_OP_LB 0x07u
+#define MMIPS32_OP_LBU 0x05u
+#define MMIPS32_OP_LHU 0x0Du
+#define MMIPS32_OP_LUI 0x0Du
+#define MMIPS32_OP_LW 0x3Fu
+#define MMIPS32_OP_LWC1 0x27u
+#define MMIPS32_OP_LDC1 0x2Fu
+#define MMIPS32_OP_MFC0 0x03u
+#define MMIPS32_OP_MFC1 0x80u
+#define MMIPS32_OP_MFHC1 0xC0u
+#define MMIPS32_OP_MTC0 0x0Bu
+#define MMIPS32_OP_MTC1 0xA0u
+#define MMIPS32_OP_MTHC1 0xE0u
+#define MMIPS32_OP_MFLO 0x075u
+#define MMIPS32_OP_MFHI 0x035u
+#define MMIPS32_OP_MTLO 0x0F5u
+#define MMIPS32_OP_MTHI 0x0B5u
+#define MMIPS32_OP_MOVN 0x018u
+#define MMIPS32_OP_ORI 0x14u
+#define MMIPS32_OP_RDHWR 0x1ACu
+#define MMIPS32_OP_SB 0x06u
+#define MMIPS32_OP_SH 0x0Eu
+#define MMIPS32_OP_SW 0x3Eu
+#define MMIPS32_OP_SWC1 0x26u
+#define MMIPS32_OP_SDC1 0x2Eu
+#define MMIPS32_OP_SLTU 0x390u
+#define MMIPS32_OP_SLL 0x000u
+#define MMIPS32_OP_SLTI 0x24u
+#define MMIPS32_OP_SRL 0x040u
+#define MMIPS32_OP_SYNCI 0x10u
+#define MMIPS32_OP_XOR 0x310u
+#define MMIPS32_OP_XORI 0x1Cu
+
+#define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
+#define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
+#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
+#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
+#define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
+
+#define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)
+#define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
+#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)
+#define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
+#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
+#define MMIPS32_CFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF)
+
+#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
+#define MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)
+#define MMIPS32_JRHB(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)
+#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
+#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
+#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
+#define MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)
+#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
+#define MMIPS32_LWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off)
+#define MMIPS32_LDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off)
+
+#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
+ MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)
+#define MMIPS32_MFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF)
+#define MMIPS32_MFHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF)
+#define MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)
+#define MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)
+#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
+ MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)
+#define MMIPS32_MTC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF)
+#define MMIPS32_MTHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF)
+#define MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)
+#define MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)
+
+#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
+#define MMIPS32_NOP 0
+#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
+#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)
+#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
+#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
+#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
+#define MMIPS32_SWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off)
+#define MMIPS32_SDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off)
+
+#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
+#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
+#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)
+#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
+#define MMIPS32_SLLV(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)
+#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
+#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */
+
+#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
+#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
+
+#define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */
+
+
+/* ejtag specific instructions */
+#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */
+#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */
+#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
+
+/* instruction code with isa selection */
+#define MIPS32_NOP 0 /* same for both isa's */
+#define MIPS32_ADDI(isa, tar, src, val) (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))
+#define MIPS32_ADDIU(isa, tar, src, val) (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))
+#define MIPS32_ADDU(isa, dst, src, tar) (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))
+#define MIPS32_AND(isa, dst, src, tar) (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))
+#define MIPS32_ANDI(isa, tar, src, val) (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))
+
+#define MIPS32_B(isa, off) (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))
+#define MIPS32_BEQ(isa, src, tar, off) (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))
+#define MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
+#define MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
+#define MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
+#define MIPS32_CFC1(isa, gpr, cpr) (isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr))
+
+#define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
+#define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
+#define MIPS32_JRHB(isa, reg) (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))
+#define MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
+#define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
+#define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
+#define MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
+#define MIPS32_LWC1(isa, reg, off, base) (isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base))
+#define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
+
+#define MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
+#define MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
+#define MIPS32_MFC1(isa, gpr, cpr) (isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr))
+#define MIPS32_MFHC1(isa, gpr, cpr) (isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr))
+#define MIPS32_MTC1(isa, gpr, cpr) (isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr))
+#define MIPS32_MTHC1(isa, gpr, cpr) (isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr))
+#define MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
+#define MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
+#define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
+#define MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
+
+#define MIPS32_MUL(isa, dst, src, t) (MIPS32_ISA_MUL(dst, src, t))
+#define MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
+#define MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
+#define MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
+#define MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
+#define MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
+#define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
+#define MIPS32_SWC1(isa, reg, off, base) (isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base))
+#define MIPS32_SDC1(isa, reg, off, base) (isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base))
+
+#define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
+#define MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))
+#define MIPS32_SLLV(isa, dst, src, sa) (MIPS32_ISA_SLLV(dst, src, sa))
+#define MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
+#define MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
+#define MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
+
+#define MIPS32_SYNCI(isa, off, base) (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))
+#define MIPS32_SYNC(isa) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)
+#define MIPS32_XOR(isa, reg, val1, val2) (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))
+#define MIPS32_XORI(isa, tar, src, val) (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))
+
+#define MIPS32_SYNCI_STEP 0x1
+
+/* ejtag specific instructions */
+#define MIPS32_DRET(isa) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)
+#define MIPS32_SDBBP(isa) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)
+
+#define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
+
+/* ejtag specific instructions */
+#define MICRO_MIPS32_SDBBP 0x000046C0
+#define MICRO_MIPS_SDBBP 0x46C0
+#define MIPS32_DSP_ENABLE 0x1000000
+
+#define MIPS32_S_INST(rs, rac, opcode) \
+ (((rs) << 21) | ((rac) << 11) | (opcode))
+
+#define MIPS32_DSP_R_INST(rt, immd, opcode, extrw) \
+ ((0x1F << 26) | ((immd) << 16) | ((rt) << 11) | ((opcode) << 6) | (extrw))
+#define MIPS32_DSP_W_INST(rs, immd, opcode, extrw) \
+ ((0x1F << 26) | ((rs) << 21) | ((immd) << 11) | ((opcode) << 6) | (extrw))
+
+#define MIPS32_DSP_MFHI(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI)
+#define MIPS32_DSP_MFLO(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO)
+#define MIPS32_DSP_MTLO(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO)
+#define MIPS32_DSP_MTHI(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI)
+#define MIPS32_DSP_RDDSP(rt, mask) MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38)
+#define MIPS32_DSP_WRDSP(rs, mask) MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38)
+
+
+/*
+ * MIPS32 Config1 Register (CP0 Register 16, Select 1)
+ */
+#define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */
+#define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */
+#define MIPS32_CFG1_MMUSSHIFT 25
+#define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */
+#define MIPS32_CFG1_ISSHIFT 22
+#define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */
+#define MIPS32_CFG1_ILSHIFT 19
+#define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */
+#define MIPS32_CFG1_IASHIFT 16
+#define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */
+#define MIPS32_CFG1_DSSHIFT 13
+#define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */
+#define MIPS32_CFG1_DLSHIFT 10
+#define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */
+#define MIPS32_CFG1_DASHIFT 7
+#define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */
+#define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */
+#define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */
+#define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */
+#define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */
+#define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */
+#define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */
+
+/*
+ * MIPS32 Coprocessor 0 register numbers
+ */
+#define MIPS32_C0_INDEX 0
+#define MIPS32_C0_INX 0
+#define MIPS32_C0_RANDOM 1
+#define MIPS32_C0_RAND 1
+#define MIPS32_C0_ENTRYLO0 2
+#define MIPS32_C0_TLBLO0 2
+#define MIPS32_C0_ENTRYLO1 3
+#define MIPS32_C0_TLBLO1 3
+#define MIPS32_C0_CONTEXT 4
+#define MIPS32_C0_CTXT 4
+#define MIPS32_C0_PAGEMASK 5
+#define MIPS32_C0_PAGEGRAIN (5, 1)
+#define MIPS32_C0_WIRED 6
+#define MIPS32_C0_HWRENA 7
+#define MIPS32_C0_BADVADDR 8
+#define MIPS32_C0_VADDR 8
+#define MIPS32_C0_COUNT 9
+#define MIPS32_C0_ENTRYHI 10
+#define MIPS32_C0_TLBHI 10
+#define MIPS32_C0_GUESTCTL1 10
+#define MIPS32_C0_COMPARE 11
+#define MIPS32_C0_STATUS 12
+#define MIPS32_C0_SR 12
+#define MIPS32_C0_INTCTL (12, 1)
+#define MIPS32_C0_SRSCTL (12, 2)
+#define MIPS32_C0_SRSMAP (12, 3)
+#define MIPS32_C0_CAUSE 13
+#define MIPS32_C0_CR 13
+#define MIPS32_C0_EPC 14
+#define MIPS32_C0_PRID 15
+#define MIPS32_C0_EBASE (15, 1)
+#define MIPS32_C0_CONFIG 16
+#define MIPS32_C0_CONFIG0 (16, 0)
+#define MIPS32_C0_CONFIG1 (16, 1)
+#define MIPS32_C0_CONFIG2 (16, 2)
+#define MIPS32_C0_CONFIG3 (16, 3)
+#define MIPS32_C0_LLADDR 17
+#define MIPS32_C0_WATCHLO 18
+#define MIPS32_C0_WATCHHI 19
+#define MIPS32_C0_DEBUG 23
+#define MIPS32_C0_DEPC 24
+#define MIPS32_C0_PERFCNT 25
+#define MIPS32_C0_ERRCTL 26
+#define MIPS32_C0_CACHEERR 27
+#define MIPS32_C0_TAGLO 28
+#define MIPS32_C0_ITAGLO 28
+#define MIPS32_C0_DTAGLO (28, 2)
+#define MIPS32_C0_TAGLO2 (28, 4)
+#define MIPS32_C0_DATALO (28, 1)
+#define MIPS32_C0_IDATALO (28, 1)
+#define MIPS32_C0_DDATALO (28, 3)
+#define MIPS32_C0_DATALO2 (28, 5)
+#define MIPS32_C0_TAGHI 29
+#define MIPS32_C0_ITAGHI 29
+#define MIPS32_C0_DATAHI (29, 1)
+#define MIPS32_C0_ERRPC 30
+#define MIPS32_C0_DESAVE 31
+
+/*
+ * MIPS32 MMU types
+ */
+#define MIPS32_MMU_TLB 1
+#define MIPS32_MMU_BAT 2
+#define MIPS32_MMU_FIXED 3
+#define MIPS32_MMU_DUAL_VTLB_FTLB 4