+{
+ int retval, tmp;
+ struct target *target = get_current_target(CMD_CTX);
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+
+
+ retval = mips32_verify_pointer(CMD, mips32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ switch (CMD_ARGC) {
+ case 0: /* No arg => print out all cp0 regs */
+ retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask);
+ break;
+ case 1: /* 1 arg => get cp0 #reg/#sel value by name */
+ retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask);
+ break;
+ case 2: /* 2 args => get cp0 reg/sel value or set value by name */
+ tmp = *CMD_ARGV[0];
+ if (isdigit(tmp)) /* starts from number then args are #reg and #sel */
+ retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info);
+ else /* or set value by register name */
+ retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info);
+
+ break;
+ case 3: /* 3 args => set cp0 reg/sel value*/
+ retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info);
+ break;
+ default: /* Other argc => err */
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
+ break;
+ }
+
+ return retval;
+}
+
+/**
+ * mips32_dsp_enable - Enable access to DSP registers
+ * @param[in] ctx: Context information for the pracc queue
+ * @param[in] isa: Instruction Set Architecture identifier
+ *
+ * @brief Enables access to DSP registers by modifying the status register.
+ *
+ * This function adds instructions to the context queue for enabling
+ * access to DSP registers by modifying the status register.
+ */
+static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
+{
+ /* Save Status Register */
+ /* move status to $9 (t1) 2*/
+ pracc_add(ctx, 0, MIPS32_MFC0(isa, 9, 12, 0));
+
+ /* Read it again in order to modify it */
+ /* move status to $0 (t0) 3*/
+ pracc_add(ctx, 0, MIPS32_MFC0(isa, 8, 12, 0));
+
+ /* Enable access to DSP registers by setting MX bit in status register */
+ /* $15 = MIPS32_PRACC_STACK 4/5/6*/
+ pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE)));
+ pracc_add(ctx, 0, MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_DSP_ENABLE)));
+ pracc_add(ctx, 0, MIPS32_ISA_OR(8, 8, 15));
+ /* Enable DSP - update status registers 7*/
+ pracc_add(ctx, 0, MIPS32_MTC0(isa, 8, 12, 0));
+}
+
+/**
+ * mips32_dsp_restore - Restore DSP status registers to the previous setting
+ * @param[in] ctx: Context information pracc queue
+ * @param[in] isa: isa identifier
+ *
+ * @brief Restores the DSP status registers to their previous setting.
+ *
+ * This function adds instructions to the context queue for restoring the DSP
+ * status registers to their values before the operation.
+ */
+static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
+{
+ pracc_add(ctx, 0, MIPS32_MTC0(isa, 9, 12, 0)); /* Restore status registers to previous setting */
+ pracc_add(ctx, 0, MIPS32_NOP); /* nop */
+}
+
+/**
+ * mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register
+ * @param[in] ejtag_info: EJTAG information structure
+ * @param[out] val: Pointer to store the read value
+ * @param[in] reg: Index of the DSP register to read
+ *
+ * @brief Reads the value from the specified MIPS32 DSP register using EJTAG access.
+ *
+ * This function initiates a sequence of instructions to read the value from the
+ * specified DSP register. It will enable dsp module if its not enabled
+ * and restoring the status registers after the read operation.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
+{
+ int isa = 0;
+
+ struct pracc_queue_info ctx = {
+ .max_code = 48,
+ .ejtag_info = ejtag_info
+ };
+
+ uint32_t dsp_read_code[] = {
+ MIPS32_MFHI(isa, t0), /* mfhi t0 ($ac0) - OPCODE - 0x00004010 */
+ MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */
+ MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
+ MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
+ MIPS32_MFLO(isa, t0), /* mflo t0 ($ac0) - OPCODE - 0x00004012 */
+ MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */
+ MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */
+ MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */
+ MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */
+ };
+
+ /* Check status register to determine if dsp register access is enabled */
+ /* Get status register so it can be restored later */
+
+ ctx.pracc_list = NULL;
+
+ /* Init context queue */
+ pracc_queue_init(&ctx);
+
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ /* Enables DSP whether its already enabled or not */
+ mips32_dsp_enable(&ctx, isa);
+
+ /* move AC or Control to $8 (t0) 8*/
+ pracc_add(&ctx, 0, dsp_read_code[reg]);
+ /* Restore status registers to previous setting */
+ mips32_dsp_restore(&ctx, isa);
+
+ /* $15 = MIPS32_PRACC_BASE_ADDR 1*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR));
+ /* store $8 to pracc_out 10*/
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(isa, 8, PRACC_OUT_OFFSET, 15));
+ /* move COP0 DeSave to $15 11*/
+ pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
+ /* restore upper 16 of $8 12*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
+ /* restore lower 16 of $8 13*/
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
+ /* restore upper 16 of $9 14*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
+ pracc_add(&ctx, 0, MIPS32_SYNC(isa));
+ /* jump to start 18*/
+ pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
+ /* restore lower 16 of $9 15*/
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+/**
+ * mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register
+ * @param[in] ejtag_info: EJTAG information structure
+ * @param[in] val: Value to be written to the register
+ * @param[in] reg: Index of the DSP register to write
+ *
+ * @brief Writes the specified value to the specified MIPS32 DSP register.
+ *
+ * This function initiates a sequence of instructions to write the given value to the
+ * specified DSP register.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
+{
+ int isa = 0;
+
+ struct pracc_queue_info ctx = {
+ .max_code = 48,
+ .ejtag_info = ejtag_info
+ };
+
+ uint32_t dsp_write_code[] = {
+ MIPS32_MTHI(isa, t0), /* mthi t0 ($ac0) - OPCODE - 0x01000011 */
+ MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */
+ MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
+ MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
+ MIPS32_MTLO(isa, t0), /* mtlo t0 ($ac0) - OPCODE - 0x01000013 */
+ MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */
+ MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */
+ MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */
+ MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/
+ };
+
+ /* Init context queue */
+ pracc_queue_init(&ctx);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ /* Enables DSP whether its already enabled or not */
+ mips32_dsp_enable(&ctx, isa);
+
+ /* Load val to $8 (t0) */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val)));
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(val)));
+
+ /* move AC or Control to $8 (t0) */
+ pracc_add(&ctx, 0, dsp_write_code[reg]);
+
+ /* nop, delay in order to ensure write */
+ pracc_add(&ctx, 0, MIPS32_NOP);
+ /* Restore status registers to previous setting */
+ mips32_dsp_restore(&ctx, isa);
+
+ /* move COP0 DeSave to $15 */
+ pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
+
+ /* restore $8 */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
+
+ /* restore upper 16 of $9 */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
+
+ /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
+ /* restore lower 16 of $9 */
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+/**
+ * mips32_handle_cpuinfo_command - Handles the 'cpuinfo' command.
+ * @param[in] cmd: Command invocation context.
+ *
+ * @brief Executes the 'cpuinfo' command which displays detailed information about the current CPU core.
+ * This includes core type, vendor, instruction set, cache size, and other relevant details.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+COMMAND_HANDLER(mips32_handle_cpuinfo_command)