jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8bb852f4f8142d918cfa799aedd37a8d9a5855a9..4894cabf8bcd1d03e767810dd3bd7b65e581e657 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1106,6 +1106,7 @@ static int cortex_m_poll(struct target *target)
 
 static int cortex_m_halt_one(struct target *target)
 {
+       int retval;
        LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
        if (target->state == TARGET_HALTED) {
@@ -1116,22 +1117,8 @@ static int cortex_m_halt_one(struct target *target)
        if (target->state == TARGET_UNKNOWN)
                LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
 
-       if (target->state == TARGET_RESET) {
-               if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
-                       LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
-                       return ERROR_TARGET_FAILURE;
-               } else {
-                       /* we came here in a reset_halt or reset_init sequence
-                        * debug entry was already prepared in cortex_m3_assert_reset()
-                        */
-                       target->debug_reason = DBG_REASON_DBGRQ;
-
-                       return ERROR_OK;
-               }
-       }
-
        /* Write to Debug Halting Control and Status Register */
-       cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+       retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 
        /* Do this really early to minimize the window where the MASKINTS erratum
         * can pile up pending interrupts. */
@@ -1139,7 +1126,7 @@ static int cortex_m_halt_one(struct target *target)
 
        target->debug_reason = DBG_REASON_DBGRQ;
 
-       return ERROR_OK;
+       return retval;
 }
 
 static int cortex_m_halt(struct target *target)
@@ -1620,7 +1607,7 @@ static int cortex_m_assert_reset(struct target *target)
        }
 
        /* some cores support connecting while srst is asserted
-        * use that mode is it has been configured */
+        * use that mode if it has been configured */
 
        bool srst_asserted = false;
 
@@ -1706,9 +1693,8 @@ static int cortex_m_assert_reset(struct target *target)
                /* srst is asserted, ignore AP access errors */
                retval = ERROR_OK;
        } else {
-               /* Use a standard Cortex-M3 software reset mechanism.
-                * We default to using VECTRESET as it is supported on all current cores
-                * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
+               /* Use a standard Cortex-M software reset mechanism.
+                * We default to using VECTRESET.
                 * This has the disadvantage of not resetting the peripherals, so a
                 * reset-init event handler is needed to perform any peripheral resets.
                 */
@@ -1755,17 +1741,7 @@ static int cortex_m_assert_reset(struct target *target)
 
        register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
-       /* now return stored error code if any */
-       if (retval != ERROR_OK)
-               return retval;
-
-       if (target->reset_halt && target_was_examined(target)) {
-               retval = target_halt(target);
-               if (retval != ERROR_OK)
-                       return retval;
-       }
-
-       return ERROR_OK;
+       return retval;
 }
 
 static int cortex_m_deassert_reset(struct target *target)
@@ -2808,7 +2784,7 @@ static int cortex_m_init_arch_info(struct target *target,
        armv7m_init_arch_info(target, armv7m);
 
        /* default reset mode is to use srst if fitted
-        * if not it will use CORTEX_M3_RESET_VECTRESET */
+        * if not it will use CORTEX_M_RESET_VECTRESET */
        cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
 
        armv7m->arm.dap = dap;
@@ -2865,8 +2841,7 @@ static int cortex_m_verify_pointer(struct command_invocation *cmd,
 
 /*
  * Only stuff below this line should need to verify that its target
- * is a Cortex-M3.  Everything else should have indirected through the
- * cortexm3_target structure, which is only used with CM3 targets.
+ * is a Cortex-M with available DAP access (not a HLA adapter).
  */
 
 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
@@ -2925,7 +2900,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
                                break;
                        }
                        if (i == ARRAY_SIZE(vec_ids)) {
-                               LOG_TARGET_ERROR(target, "No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
+                               LOG_TARGET_ERROR(target, "No Cortex-M vector '%s'", CMD_ARGV[CMD_ARGC]);
                                return ERROR_COMMAND_SYNTAX_ERROR;
                        }
                }