jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv8_dpm.c
index fcd4d5971e9d87b2cba8d1312785a24642b5fe41..8bb24f225b89efae6f73948e22eec27f509fadb3 100644 (file)
@@ -46,7 +46,7 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
        dpm->last_el = el;
 
        /* In Debug state, each bit gives the current Execution state of each EL */
-       if ((rw >> el) & 0b1)
+       if ((rw >> el) & 1)
                return ARM_STATE_AARCH64;
 
        return ARM_STATE_ARM;
@@ -274,7 +274,7 @@ static int dpmv8_instr_write_data_dcc(struct arm_dpm *dpm,
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_exec_opcode(dpm, opcode, 0);
+       return dpmv8_exec_opcode(dpm, opcode, NULL);
 }
 
 static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
@@ -287,7 +287,7 @@ static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_exec_opcode(dpm, opcode, 0);
+       return dpmv8_exec_opcode(dpm, opcode, NULL);
 }
 
 static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm,
@@ -725,7 +725,8 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /**
- * Read basic registers of the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR in AArch32
+ * state or R0 to R31, PC and CPSR in AArch64 state;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
@@ -772,9 +773,15 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
        /* update core mode and state */
        armv8_set_cpsr(arm, cpsr);
 
-       for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
+       /* read the remaining registers that would be required by GDB 'g' packet */
+       for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) {
                struct arm_reg *arm_reg;
 
+               /* in AArch32 skip AArch64 registers */
+               /* TODO: this should be detected below through arm_reg->mode */
+               if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
+                       continue;
+
                r = armv8_reg_current(arm, i);
                if (!r->exist || r->valid)
                        continue;
@@ -1210,7 +1217,7 @@ static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
        uint32_t control;
 
        /* this hardware doesn't support data value matching or masking */
-       if (wp->value || wp->mask != ~(uint32_t)0) {
+       if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
                LOG_DEBUG("watchpoint values and masking not supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }

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