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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv8_dpm.c
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 6ef8c33de2d07fa6e34559fbab98cab54d4e92f9..8bb24f225b89efae6f73948e22eec27f509fadb3 100644 (file)
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /*
  * Copyright (C) 2009 by David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  */
 
 #ifdef HAVE_CONFIG_H
@@ -55,7 +46,7 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
        dpm->last_el = el;
 
        /* In Debug state, each bit gives the current Execution state of each EL */
-       if ((rw >> el) & 0b1)
+       if ((rw >> el) & 1)
                return ARM_STATE_AARCH64;
 
        return ARM_STATE_ARM;
@@ -283,7 +274,7 @@ static int dpmv8_instr_write_data_dcc(struct arm_dpm *dpm,
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_exec_opcode(dpm, opcode, 0);
+       return dpmv8_exec_opcode(dpm, opcode, NULL);
 }
 
 static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
@@ -296,7 +287,7 @@ static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_exec_opcode(dpm, opcode, 0);
+       return dpmv8_exec_opcode(dpm, opcode, NULL);
 }
 
 static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm,
@@ -490,7 +481,7 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 
 /* Read coprocessor */
 static int dpmv8_mrc(struct target *target, int cpnum,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+       uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
        uint32_t *value)
 {
        struct arm *arm = target_to_arm(target);
@@ -502,12 +493,12 @@ static int dpmv8_mrc(struct target *target, int cpnum,
                return retval;
 
        LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
+               (int) op1, (int) crn,
+               (int) crm, (int) op2);
 
        /* read coprocessor register into R0; return via DCC */
        retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
+                       ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
                        value);
 
        /* (void) */ dpm->finish(dpm);
@@ -515,7 +506,7 @@ static int dpmv8_mrc(struct target *target, int cpnum,
 }
 
 static int dpmv8_mcr(struct target *target, int cpnum,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+       uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
        uint32_t value)
 {
        struct arm *arm = target_to_arm(target);
@@ -527,12 +518,12 @@ static int dpmv8_mcr(struct target *target, int cpnum,
                return retval;
 
        LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
+               (int) op1, (int) crn,
+               (int) crm, (int) op2);
 
        /* read DCC into r0; then write coprocessor register from R0 */
        retval = dpm->instr_write_data_r0(dpm,
-                       ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
+                       ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
                        value);
 
        /* (void) */ dpm->finish(dpm);
@@ -596,6 +587,9 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
        }
 
        LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
+       if (dpm->last_el == target_el)
+               return ERROR_OK; /* nothing to do */
+
        if (target_el > dpm->last_el) {
                retval = dpm->instr_execute(dpm,
                                armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el);
@@ -610,7 +604,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
                                /* load SPSR with the desired mode and execute DRPS */
                                LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
                                retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
+                                               ARMV8_MSR_GP_XPSR_T1(1, 0, 15), cpsr);
                                if (retval == ERROR_OK)
                                        retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
                        }
@@ -731,7 +725,8 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /**
- * Read basic registers of the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR in AArch32
+ * state or R0 to R31, PC and CPSR in AArch64 state;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
@@ -778,11 +773,17 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
        /* update core mode and state */
        armv8_set_cpsr(arm, cpsr);
 
-       for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
+       /* read the remaining registers that would be required by GDB 'g' packet */
+       for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) {
                struct arm_reg *arm_reg;
 
+               /* in AArch32 skip AArch64 registers */
+               /* TODO: this should be detected below through arm_reg->mode */
+               if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
+                       continue;
+
                r = armv8_reg_current(arm, i);
-               if (r->valid)
+               if (!r->exist || r->valid)
                        continue;
 
                /* Skip reading FP-SIMD registers */
@@ -818,7 +819,7 @@ fail:
  * or running debugger code.
  */
 static int dpmv8_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
-       struct dpm_bpwp *xp, int *set_p)
+       struct dpm_bpwp *xp, bool *set_p)
 {
        int retval = ERROR_OK;
        bool disable;
@@ -892,7 +893,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                        struct breakpoint *bp = dbp->bp;
 
                        retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
-                                       bp ? &bp->set : NULL);
+                                       bp ? &bp->is_set : NULL);
                        if (retval != ERROR_OK)
                                goto done;
                }
@@ -904,7 +905,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                struct watchpoint *wp = dwp->wp;
 
                retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
-                               wp ? &wp->set : NULL);
+                               wp ? &wp->is_set : NULL);
                if (retval != ERROR_OK)
                        goto done;
        }
@@ -922,8 +923,11 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
        for (unsigned i = 1; i < cache->num_regs; i++) {
                struct arm_reg *r;
 
+               /* skip non-existent */
+               if (!cache->reg_list[i].exist)
+                       continue;
                /* skip PC and CPSR */
-               if (i == ARMV8_PC || i == ARMV8_xPSR)
+               if (i == ARMV8_PC || i == ARMV8_XPSR)
                        continue;
                /* skip invalid */
                if (!cache->reg_list[i].valid)
@@ -945,7 +949,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
        /* flush CPSR and PC */
        if (retval == ERROR_OK)
-               retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
+               retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR);
        if (retval == ERROR_OK)
                retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
        /* flush R0 -- it's *very* dirty by now */
@@ -1047,7 +1051,7 @@ static int armv8_dpm_full_context(struct target *target)
                for (unsigned i = 0; i < cache->num_regs; i++) {
                        struct arm_reg *r;
 
-                       if (cache->reg_list[i].valid)
+                       if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
                                continue;
                        r = cache->reg_list[i].arch_info;
 
@@ -1213,7 +1217,7 @@ static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
        uint32_t control;
 
        /* this hardware doesn't support data value matching or masking */
-       if (wp->value || wp->mask != ~(uint32_t)0) {
+       if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
                LOG_DEBUG("watchpoint values and masking not supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
@@ -1299,9 +1303,9 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
        unsigned int el;
 
        static const int clobbered_regs_by_el[3][5] = {
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
        };
 
        el = (dpm->dscr >> 8) & 3;
@@ -1316,7 +1320,7 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
        mem_ap_write_u32(armv8->debug_ap,
                armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 
-       armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
+       armv8->read_reg_u64(armv8, ARMV8_XPSR, &dlr);
        dspsr = dlr;
        armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
 
@@ -1407,7 +1411,7 @@ int armv8_dpm_setup(struct arm_dpm *dpm)
        arm->read_core_reg = armv8_dpm_read_core_reg;
        arm->write_core_reg = armv8_dpm_write_core_reg;
 
-       if (arm->core_cache == NULL) {
+       if (!arm->core_cache) {
                cache = armv8_build_reg_cache(target);
                if (!cache)
                        return ERROR_FAIL;
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