-/* SPDX-License-Identifier: GPL-2.0-or-later */
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2009 by David Brownell
dpm->last_el = el;
/* In Debug state, each bit gives the current Execution state of each EL */
- if ((rw >> el) & 0b1)
+ if ((rw >> el) & 1)
return ARM_STATE_AARCH64;
return ARM_STATE_ARM;
if (retval != ERROR_OK)
return retval;
- return dpmv8_exec_opcode(dpm, opcode, 0);
+ return dpmv8_exec_opcode(dpm, opcode, NULL);
}
static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
if (retval != ERROR_OK)
return retval;
- return dpmv8_exec_opcode(dpm, opcode, 0);
+ return dpmv8_exec_opcode(dpm, opcode, NULL);
}
static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm,
}
LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
+ if (dpm->last_el == target_el)
+ return ERROR_OK; /* nothing to do */
+
if (target_el > dpm->last_el) {
retval = dpm->instr_execute(dpm,
armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el);
/* load SPSR with the desired mode and execute DRPS */
LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15), cpsr);
if (retval == ERROR_OK)
retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
}
}
/**
- * Read basic registers of the current context: R0 to R15, and CPSR;
+ * Read basic registers of the current context: R0 to R15, and CPSR in AArch32
+ * state or R0 to R31, PC and CPSR in AArch64 state;
* sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
* In normal operation this is called on entry to halting debug state,
* possibly after some other operations supporting restore of debug state
/* update core mode and state */
armv8_set_cpsr(arm, cpsr);
- for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
+ /* read the remaining registers that would be required by GDB 'g' packet */
+ for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) {
struct arm_reg *arm_reg;
+ /* in AArch32 skip AArch64 registers */
+ /* TODO: this should be detected below through arm_reg->mode */
+ if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
+ continue;
+
r = armv8_reg_current(arm, i);
if (!r->exist || r->valid)
continue;
if (!cache->reg_list[i].exist)
continue;
/* skip PC and CPSR */
- if (i == ARMV8_PC || i == ARMV8_xPSR)
+ if (i == ARMV8_PC || i == ARMV8_XPSR)
continue;
/* skip invalid */
if (!cache->reg_list[i].valid)
/* flush CPSR and PC */
if (retval == ERROR_OK)
- retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
+ retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR);
if (retval == ERROR_OK)
retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
/* flush R0 -- it's *very* dirty by now */
uint32_t control;
/* this hardware doesn't support data value matching or masking */
- if (wp->value || wp->mask != ~(uint32_t)0) {
+ if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
LOG_DEBUG("watchpoint values and masking not supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
unsigned int el;
static const int clobbered_regs_by_el[3][5] = {
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
};
el = (dpm->dscr >> 8) & 3;
mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
- armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
+ armv8->read_reg_u64(armv8, ARMV8_XPSR, &dlr);
dspsr = dlr;
armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);