+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2008 by Oyvind Harboe *
* oyvind.harboe@zylin.com *
* *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * Copyright (C) 2018 by Liviu Ionescu *
+ * <ilg@livius.net> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include <helper/binarybuffer.h>
#include "algorithm.h"
#include "register.h"
+#include "semihosting_common.h"
/* offsets into armv4_5 core register cache */
enum {
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 41,
+ ARM_SPSR_HYP = 43,
};
static const uint8_t arm_usr_indices[17] = {
39, 40, ARM_SPSR_MON,
};
+static const uint8_t arm_hyp_indices[2] = {
+ 42, ARM_SPSR_HYP,
+};
+
static const struct {
const char *name;
unsigned short psr;
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
},
+ {
+ .name = "Secure Monitor ARM1176JZF-S",
+ .psr = ARM_MODE_1176_MON,
+ .n_indices = ARRAY_SIZE(arm_mon_indices),
+ .indices = arm_mon_indices,
+ },
/* These special modes are currently only supported
* by ARMv6M and ARMv7M profiles */
.name = "Handler",
.psr = ARM_MODE_HANDLER,
},
+
+ /* armv7-a with virtualization extension */
+ {
+ .name = "Hypervisor",
+ .psr = ARM_MODE_HYP,
+ .n_indices = ARRAY_SIZE(arm_hyp_indices),
+ .indices = arm_hyp_indices,
+ },
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
case ARM_MODE_SYS:
return 6;
case ARM_MODE_MON:
+ case ARM_MODE_1176_MON:
return 7;
+ case ARM_MODE_HYP:
+ return 8;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;
return ARM_MODE_SYS;
case 7:
return ARM_MODE_MON;
+ case 8:
+ return ARM_MODE_HYP;
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARM_MODE_ANY;
* correspond to r0..r7, and the fifteenth to PC, so that callers
* don't need to map them.
*/
- { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
- { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
- { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
- { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
- { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
- { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
- { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
- { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
+ [0] = { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
+ [1] = { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
+ [2] = { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
+ [3] = { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
+ [4] = { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
+ [5] = { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
+ [6] = { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
+ [7] = { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
* them as MODE_ANY creates special cases. (ANY means
* "not mapped" elsewhere; here it's "everything but FIQ".)
*/
- { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
- { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
- { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
- { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
- { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
+ [8] = { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
+ [9] = { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
+ [10] = { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
+ [11] = { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
+ [12] = { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
/* Historical GDB mapping of indices:
* - 13-14 are sp and lr, but banked counterparts are used
*/
/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
- { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
- { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
+ [13] = { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
+ [14] = { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
/* guaranteed to be at index 15 */
- { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
- { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
- { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
- { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
- { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
- { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
+ [15] = { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
+ [16] = { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
+ [17] = { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
+ [18] = { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
+ [19] = { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
+ [20] = { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
- { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
- { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
+ [21] = { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
+ [22] = { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
- { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
- { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
+ [23] = { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
+ [24] = { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
- { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
- { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
+ [25] = { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
+ [26] = { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
- { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
- { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
+ [27] = { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
+ [28] = { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
- { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
- { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
+ [29] = { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
+ [30] = { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
- { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
- { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
- { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
- { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
- { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
- { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
+ [31] = { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
+ [32] = { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
+ [33] = { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
+ [34] = { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
+ [35] = { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
+ [36] = { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
/* These are only used for GDB target description, banked registers are accessed instead */
- { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
- { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
+ [37] = { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
+ [38] = { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
/* These exist only when the Security Extension (TrustZone) is present */
- { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
- { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
- { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
+ [39] = { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
+ [40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
+ [41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
+ /* These exist only when the Virtualization Extensions is present */
+ [42] = { .name = "sp_hyp", .cookie = 13, .mode = ARM_MODE_HYP, .gdb_index = 51, },
+ [43] = { .name = "spsr_hyp", .cookie = 16, .mode = ARM_MODE_HYP, .gdb_index = 52, },
+};
+
+static const struct {
+ unsigned int id;
+ const char *name;
+ uint32_t bits;
+ enum arm_mode mode;
+ enum reg_type type;
+ const char *group;
+ const char *feature;
+} arm_vfp_v3_regs[] = {
+ { ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
};
/* map core mode (USR, FIQ, ...) and register number to
* indices into the register cache
*/
-const int armv4_5_core_reg_map[8][17] = {
+const int armv4_5_core_reg_map[9][17] = {
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
{ /* MON */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
+ },
+ { /* HYP */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
}
};
*/
if (arm->cpsr) {
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
- arm->cpsr->valid = 1;
- arm->cpsr->dirty = 0;
+ arm->cpsr->valid = true;
+ arm->cpsr->dirty = false;
}
arm->core_mode = mode;
* Modern ARM cores use Vector Floating Point (VFP), if they
* have any floating point support. VFP is not FPA-compatible.
*/
-struct reg arm_gdb_dummy_fp_reg = {
+static struct reg arm_gdb_dummy_fp_reg = {
.name = "GDB dummy FPA register",
.value = (uint8_t *) arm_gdb_dummy_fp_value,
- .valid = 1,
+ .valid = true,
.size = 96,
.exist = false,
.number = 16,
* Dummy FPA status registers are required to support GDB on ARM.
* Register packets require an obsolete FPA status register.
*/
-struct reg arm_gdb_dummy_fps_reg = {
+static struct reg arm_gdb_dummy_fps_reg = {
.name = "GDB dummy FPA status register",
.value = (uint8_t *) arm_gdb_dummy_fps_value,
- .valid = 1,
+ .valid = true,
.size = 32,
.exist = false,
.number = 24,
struct target *target = reg_arch_info->target;
if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
+ LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
retval = reg_arch_info->arm->read_core_reg(target, reg,
reg_arch_info->num, reg_arch_info->mode);
if (retval == ERROR_OK) {
- reg->valid = 1;
- reg->dirty = 0;
+ reg->valid = true;
+ reg->dirty = false;
}
return retval;
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
+ LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
+ uint8_t t[4];
+ buf_set_u32(t, 0, 32, value);
armv4_5_target->write_core_reg(target, reg,
- 16, ARM_MODE_ANY, value);
+ 16, ARM_MODE_ANY, t);
}
} else {
buf_set_u32(reg->value, 0, 32, value);
- reg->valid = 1;
+ if (reg->size == 64) {
+ value = buf_get_u32(buf + 4, 0, 32);
+ buf_set_u32(reg->value + 4, 0, 32, value);
+ }
+ reg->valid = true;
}
- reg->dirty = 1;
+ reg->dirty = true;
return ERROR_OK;
}
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
+ int num_core_regs = num_regs;
+ if (arm->arm_vfp_version == ARM_VFP_V3)
+ num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
+
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
cache->reg_list = reg_list;
cache->num_regs = 0;
- for (i = 0; i < num_regs; i++) {
+ for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
reg_arch_info[i].target = target;
reg_arch_info[i].arm = arm;
- reg_list[i].name = (char *) arm_core_regs[i].name;
+ reg_list[i].name = arm_core_regs[i].name;
reg_list[i].number = arm_core_regs[i].gdb_index;
reg_list[i].size = 32;
- reg_list[i].value = ®_arch_info[i].value;
+ reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = ®_arch_info[i];
reg_list[i].exist = true;
cache->num_regs++;
}
+ int j;
+ for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
+ reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
+ reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
+ reg_arch_info[i].target = target;
+ reg_arch_info[i].arm = arm;
+
+ reg_list[i].name = arm_vfp_v3_regs[j].name;
+ reg_list[i].number = arm_vfp_v3_regs[j].id;
+ reg_list[i].size = arm_vfp_v3_regs[j].bits;
+ reg_list[i].value = reg_arch_info[i].value;
+ reg_list[i].type = &arm_reg_type;
+ reg_list[i].arch_info = ®_arch_info[i];
+ reg_list[i].exist = true;
+
+ reg_list[i].caller_save = false;
+
+ reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
+ reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
+
+ reg_list[i].feature = malloc(sizeof(struct reg_feature));
+ reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
+
+ reg_list[i].group = arm_vfp_v3_regs[j].group;
+
+ cache->num_regs++;
+ }
+
arm->pc = reg_list + 15;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
+
return cache;
}
+void arm_free_reg_cache(struct arm *arm)
+{
+ if (!arm || !arm->core_cache)
+ return;
+
+ struct reg_cache *cache = arm->core_cache;
+
+ for (unsigned int i = 0; i < cache->num_regs; i++) {
+ struct reg *reg = &cache->reg_list[i];
+
+ free(reg->feature);
+ free(reg->reg_data_type);
+ }
+
+ free(cache->reg_list[0].arch_info);
+ free(cache->reg_list);
+ free(cache);
+
+ arm->core_cache = NULL;
+}
+
int arm_arch_state(struct target *target)
{
struct arm *arm = target_to_arm(target);
return ERROR_FAIL;
}
+ /* avoid filling log waiting for fileio reply */
+ if (target->semihosting && target->semihosting->hit_fileio)
+ return ERROR_OK;
+
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
arm_state_strings[arm->core_state],
debug_reason_name(target),
arm_mode_name(arm->core_mode),
buf_get_u32(arm->cpsr->value, 0, 32),
buf_get_u32(arm->pc->value, 0, 32),
- arm->is_semihosting ? ", semihosting" : "");
+ (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
+ (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
return ERROR_OK;
}
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
- (cache->reg_list[armv4_5_core_reg_map[mode][num]])
-
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
struct reg *regs;
if (!is_arm(arm)) {
- command_print(CMD_CTX, "current target isn't an ARM");
+ command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "error: target must be halted for register accesses");
- return ERROR_FAIL;
+ command_print(CMD, "Error: target must be halted for register accesses");
+ return ERROR_TARGET_NOT_HALTED;
}
- if (arm->core_type != ARM_MODE_ANY) {
- command_print(CMD_CTX,
+ if (arm->core_type != ARM_CORE_TYPE_STD) {
+ command_print(CMD,
"Microcontroller Profile not supported - use standard reg cmd");
return ERROR_OK;
}
}
if (!arm->full_context) {
- command_print(CMD_CTX, "error: target doesn't support %s",
+ command_print(CMD, "Error: target doesn't support %s",
CMD_NAME);
return ERROR_FAIL;
}
char *sep = "\n";
char *shadow = "";
+ if (!arm_mode_data[mode].n_indices)
+ continue;
+
/* label this bank of registers (or shadows) */
switch (arm_mode_data[mode].psr) {
case ARM_MODE_SYS:
name = "System and User";
sep = "";
break;
+ case ARM_MODE_HYP:
+ if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ /* FALLTHROUGH */
case ARM_MODE_MON:
- if (arm->core_type != ARM_MODE_MON)
+ case ARM_MODE_1176_MON:
+ if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* FALLTHROUGH */
default:
shadow = "shadow ";
break;
}
- command_print(CMD_CTX, "%s%s mode %sregisters",
+ command_print(CMD, "%s%s mode %sregisters",
sep, name, shadow);
/* display N rows of up to 4 registers each */
"%8s: %8.8" PRIx32 " ",
reg->name, value);
}
- command_print(CMD_CTX, "%s", output);
+ command_print(CMD, "%s", output);
}
}
return ERROR_OK;
}
-COMMAND_HANDLER(handle_armv4_5_core_state_command)
+COMMAND_HANDLER(handle_arm_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target_to_arm(target);
+ int ret = ERROR_OK;
if (!is_arm(arm)) {
- command_print(CMD_CTX, "current target isn't an ARM");
+ command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
- /* armv7m not supported */
- command_print(CMD_CTX, "Unsupported Command");
- return ERROR_OK;
- }
-
if (CMD_ARGC > 0) {
- if (strcmp(CMD_ARGV[0], "arm") == 0)
- arm->core_state = ARM_STATE_ARM;
+ if (strcmp(CMD_ARGV[0], "arm") == 0) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
+ command_print(CMD, "arm mode not supported on Cortex-M");
+ ret = ERROR_FAIL;
+ } else {
+ arm->core_state = ARM_STATE_ARM;
+ }
+ }
if (strcmp(CMD_ARGV[0], "thumb") == 0)
arm->core_state = ARM_STATE_THUMB;
}
- command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
+ command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
- return ERROR_OK;
+ return ret;
}
COMMAND_HANDLER(handle_arm_disassemble_command)
{
- int retval = ERROR_OK;
+#if HAVE_CAPSTONE
struct target *target = get_current_target(CMD_CTX);
- if (target == NULL) {
+ if (!target) {
LOG_ERROR("No target selected");
return ERROR_FAIL;
}
struct arm *arm = target_to_arm(target);
- uint32_t address;
- int count = 1;
- int thumb = 0;
+ target_addr_t address;
+ unsigned int count = 1;
+ bool thumb = false;
if (!is_arm(arm)) {
- command_print(CMD_CTX, "current target isn't an ARM");
+ command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m is always thumb mode */
- thumb = 1;
+ thumb = true;
}
switch (CMD_ARGC) {
case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0)
- goto usage;
- thumb = 1;
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ thumb = true;
/* FALL THROUGH */
case 2:
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
/* FALL THROUGH */
case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
- command_print(CMD_CTX, "Disassemble as Thumb");
- thumb = 1;
+ command_print(CMD, "Disassemble as Thumb");
+ thumb = true;
}
address &= ~1;
}
break;
default:
-usage:
- count = 0;
- retval = ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- while (count-- > 0) {
- struct arm_instruction cur_instruction;
-
- if (thumb) {
- /* Always use Thumb2 disassembly for best handling
- * of 32-bit BL/BLX, and to work with newer cores
- * (some ARMv6, all ARMv7) that use Thumb2.
- */
- retval = thumb2_opcode(target, address,
- &cur_instruction);
- if (retval != ERROR_OK)
- break;
- } else {
- uint32_t opcode;
-
- retval = target_read_u32(target, address, &opcode);
- if (retval != ERROR_OK)
- break;
- retval = arm_evaluate_opcode(opcode, address,
- &cur_instruction) != ERROR_OK;
- if (retval != ERROR_OK)
- break;
- }
- command_print(CMD_CTX, "%s", cur_instruction.text);
- address += cur_instruction.instruction_size;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
- return retval;
+ return arm_disassemble(CMD, target, address, count, thumb);
+#else
+ command_print(CMD, "capstone disassembly framework required");
+ return ERROR_FAIL;
+#endif
}
-static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
+COMMAND_HANDLER(handle_armv4_5_mcrmrc)
{
- struct command_context *context;
- struct target *target;
- struct arm *arm;
- int retval;
+ bool is_mcr = false;
+ unsigned int arg_cnt = 5;
- context = current_command_context(interp);
- assert(context != NULL);
+ if (!strcmp(CMD_NAME, "mcr")) {
+ is_mcr = true;
+ arg_cnt = 6;
+ }
+
+ if (arg_cnt != CMD_ARGC)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- target = get_current_target(context);
- if (target == NULL) {
- LOG_ERROR("%s: no current target", __func__);
- return JIM_ERR;
+ struct target *target = get_current_target(CMD_CTX);
+ if (!target) {
+ command_print(CMD, "no current target");
+ return ERROR_FAIL;
}
if (!target_was_examined(target)) {
- LOG_ERROR("%s: not yet examined", target_name(target));
- return JIM_ERR;
+ command_print(CMD, "%s: not yet examined", target_name(target));
+ return ERROR_TARGET_NOT_EXAMINED;
}
- arm = target_to_arm(target);
+
+ struct arm *arm = target_to_arm(target);
if (!is_arm(arm)) {
- LOG_ERROR("%s: not an ARM", target_name(target));
- return JIM_ERR;
+ command_print(CMD, "%s: not an ARM", target_name(target));
+ return ERROR_FAIL;
}
- if ((argc < 6) || (argc > 7)) {
- /* FIXME use the command name to verify # params... */
- LOG_ERROR("%s: wrong number of arguments", __func__);
- return JIM_ERR;
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD, "Error: [%s] not halted", target_name(target));
+ return ERROR_TARGET_NOT_HALTED;
}
int cpnum;
uint32_t op1;
uint32_t op2;
- uint32_t CRn;
- uint32_t CRm;
+ uint32_t crn;
+ uint32_t crm;
uint32_t value;
- long l;
/* NOTE: parameter sequence matches ARM instruction set usage:
* MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
* MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
* The "rX" is necessarily omitted; it uses Tcl mechanisms.
*/
- retval = Jim_GetLong(interp, argv[1], &l);
- if (retval != JIM_OK)
- return retval;
- if (l & ~0xf) {
- LOG_ERROR("%s: %s %d out of range", __func__,
- "coprocessor", (int) l);
- return JIM_ERR;
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
+ if (cpnum & ~0xf) {
+ command_print(CMD, "coprocessor %d out of range", cpnum);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- cpnum = l;
- retval = Jim_GetLong(interp, argv[2], &l);
- if (retval != JIM_OK)
- return retval;
- if (l & ~0x7) {
- LOG_ERROR("%s: %s %d out of range", __func__,
- "op1", (int) l);
- return JIM_ERR;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
+ if (op1 & ~0x7) {
+ command_print(CMD, "op1 %d out of range", op1);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- op1 = l;
- retval = Jim_GetLong(interp, argv[3], &l);
- if (retval != JIM_OK)
- return retval;
- if (l & ~0xf) {
- LOG_ERROR("%s: %s %d out of range", __func__,
- "CRn", (int) l);
- return JIM_ERR;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn);
+ if (crn & ~0xf) {
+ command_print(CMD, "CRn %d out of range", crn);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- CRn = l;
- retval = Jim_GetLong(interp, argv[4], &l);
- if (retval != JIM_OK)
- return retval;
- if (l & ~0xf) {
- LOG_ERROR("%s: %s %d out of range", __func__,
- "CRm", (int) l);
- return JIM_ERR;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm);
+ if (crm & ~0xf) {
+ command_print(CMD, "CRm %d out of range", crm);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- CRm = l;
- retval = Jim_GetLong(interp, argv[5], &l);
- if (retval != JIM_OK)
- return retval;
- if (l & ~0x7) {
- LOG_ERROR("%s: %s %d out of range", __func__,
- "op2", (int) l);
- return JIM_ERR;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2);
+ if (op2 & ~0x7) {
+ command_print(CMD, "op2 %d out of range", op2);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- op2 = l;
-
- value = 0;
- /* FIXME don't assume "mrc" vs "mcr" from the number of params;
- * that could easily be a typo! Check both...
- *
+ /*
* FIXME change the call syntax here ... simplest to just pass
* the MRC() or MCR() instruction to be executed. That will also
* let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
* if that's ever needed.
*/
- if (argc == 7) {
- retval = Jim_GetLong(interp, argv[6], &l);
- if (retval != JIM_OK)
- return retval;
- value = l;
+ if (is_mcr) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value);
/* NOTE: parameters reordered! */
- /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
- retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
+ /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
+ int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
if (retval != ERROR_OK)
- return JIM_ERR;
+ return retval;
} else {
+ value = 0;
/* NOTE: parameters reordered! */
- /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
- retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
+ /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
+ int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
if (retval != ERROR_OK)
- return JIM_ERR;
+ return retval;
- Jim_SetResult(interp, Jim_NewIntObj(interp, value));
+ command_print(CMD, "0x%" PRIx32, value);
}
- return JIM_OK;
+ return ERROR_OK;
}
-COMMAND_HANDLER(handle_arm_semihosting_command)
+COMMAND_HANDLER(handle_armv4_5_mcrrmrrc)
{
- struct target *target = get_current_target(CMD_CTX);
+ bool is_mcrr = false;
+ unsigned int arg_cnt = 3;
- if (target == NULL) {
- LOG_ERROR("No target selected");
- return ERROR_FAIL;
+ if (!strcmp(CMD_NAME, "mcrr")) {
+ is_mcrr = true;
+ arg_cnt = 4;
}
- struct arm *arm = target_to_arm(target);
+ if (arg_cnt != CMD_ARGC)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- if (!is_arm(arm)) {
- command_print(CMD_CTX, "current target isn't an ARM");
+ struct target *target = get_current_target(CMD_CTX);
+ if (!target) {
+ command_print(CMD, "no current target");
return ERROR_FAIL;
}
+ if (!target_was_examined(target)) {
+ command_print(CMD, "%s: not yet examined", target_name(target));
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
- if (!arm->setup_semihosting) {
- command_print(CMD_CTX, "semihosting not supported for current target");
+ struct arm *arm = target_to_arm(target);
+ if (!is_arm(arm)) {
+ command_print(CMD, "%s: not an ARM", target_name(target));
return ERROR_FAIL;
}
- if (CMD_ARGC > 0) {
- int semihosting;
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+ int cpnum;
+ uint32_t op1;
+ uint32_t crm;
+ uint64_t value;
- if (!target_was_examined(target)) {
- LOG_ERROR("Target not examined yet");
- return ERROR_FAIL;
- }
+ /* NOTE: parameter sequence matches ARM instruction set usage:
+ * MCRR pNUM, op1, rX1, rX2, CRm ; write CP from rX1 and rX2
+ * MREC pNUM, op1, rX1, rX2, CRm ; read CP into rX1 and rX2
+ * The "rXn" are necessarily omitted; they use Tcl mechanisms.
+ */
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
+ if (cpnum & ~0xf) {
+ command_print(CMD, "coprocessor %d out of range", cpnum);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
- if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
- LOG_ERROR("Failed to Configure semihosting");
- return ERROR_FAIL;
- }
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
+ if (op1 & ~0xf) {
+ command_print(CMD, "op1 %d out of range", op1);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
- /* FIXME never let that "catch" be dropped! */
- arm->is_semihosting = semihosting;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crm);
+ if (crm & ~0xf) {
+ command_print(CMD, "CRm %d out of range", crm);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- command_print(CMD_CTX, "semihosting is %s",
- arm->is_semihosting
- ? "enabled" : "disabled");
+ /*
+ * FIXME change the call syntax here ... simplest to just pass
+ * the MRC() or MCR() instruction to be executed. That will also
+ * let us support the "mrrc2" and "mcrr2" opcodes (toggling one bit)
+ * if that's ever needed.
+ */
+ if (is_mcrr) {
+ COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], value);
+
+ /* NOTE: parameters reordered! */
+ /* ARMV5_T_MCRR(cpnum, op1, crm) */
+ int retval = arm->mcrr(target, cpnum, op1, crm, value);
+ if (retval != ERROR_OK)
+ return retval;
+ } else {
+ value = 0;
+ /* NOTE: parameters reordered! */
+ /* ARMV5_T_MRRC(cpnum, op1, crm) */
+ int retval = arm->mrrc(target, cpnum, op1, crm, &value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD, "0x%" PRIx64, value);
+ }
return ERROR_OK;
}
.help = "display ARM core registers",
.usage = "",
},
- {
- .name = "core_state",
- .handler = handle_armv4_5_core_state_command,
- .mode = COMMAND_EXEC,
- .usage = "['arm'|'thumb']",
- .help = "display/change ARM core state",
- },
- {
- .name = "disassemble",
- .handler = handle_arm_disassemble_command,
- .mode = COMMAND_EXEC,
- .usage = "address [count ['thumb']]",
- .help = "disassemble instructions ",
- },
{
.name = "mcr",
.mode = COMMAND_EXEC,
- .jim_handler = &jim_mcrmrc,
+ .handler = handle_armv4_5_mcrmrc,
.help = "write coprocessor register",
.usage = "cpnum op1 CRn CRm op2 value",
},
{
.name = "mrc",
- .jim_handler = &jim_mcrmrc,
+ .mode = COMMAND_EXEC,
+ .handler = handle_armv4_5_mcrmrc,
.help = "read coprocessor register",
.usage = "cpnum op1 CRn CRm op2",
},
{
- "semihosting",
- .handler = handle_arm_semihosting_command,
+ .name = "mcrr",
.mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting operations",
+ .handler = handle_armv4_5_mcrrmrrc,
+ .help = "write coprocessor 64-bit register",
+ .usage = "cpnum op1 CRm value",
},
+ {
+ .name = "mrrc",
+ .mode = COMMAND_EXEC,
+ .handler = handle_armv4_5_mcrrmrrc,
+ .help = "read coprocessor 64-bit register",
+ .usage = "cpnum op1 CRm",
+ },
+ {
+ .chain = arm_all_profiles_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm_all_profiles_command_handlers[] = {
+ {
+ .name = "core_state",
+ .handler = handle_arm_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['arm'|'thumb']",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = handle_arm_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address [count ['thumb']]",
+ .help = "disassemble instructions",
+ },
+ {
+ .chain = semihosting_common_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
+
const struct command_registration arm_command_handlers[] = {
{
.name = "arm",
COMMAND_REGISTRATION_DONE
};
+/*
+ * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
+ * of arm architecture. You can list them using the autocompletion of gdb
+ * command prompt by typing "set architecture " and then press TAB key.
+ * The default, selected automatically, is "arm".
+ * Let's use the default value, here, to make gdb-multiarch behave in the
+ * same way as a gdb for arm. This can be changed later on. User can still
+ * set the specific architecture variant with the gdb command.
+ */
+const char *arm_get_gdb_arch(const struct target *target)
+{
+ return "arm";
+}
+
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class)
(*reg_list)[25] = arm->cpsr;
return ERROR_OK;
- break;
case REG_CLASS_ALL:
- *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ switch (arm->core_type) {
+ case ARM_CORE_TYPE_SEC_EXT:
+ *reg_list_size = 51;
+ break;
+ case ARM_CORE_TYPE_VIRT_EXT:
+ *reg_list_size = 53;
+ break;
+ default:
+ *reg_list_size = 48;
+ }
+ unsigned int list_size_core = *reg_list_size;
+ if (arm->arm_vfp_version == ARM_VFP_V3)
+ *reg_list_size += 33;
+
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
- if (!(arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON))
- (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+
+ if (arm_core_regs[i].mode == ARM_MODE_MON
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}
/* When we supply the target description, there is no need for fake FPA */
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[24]->size = 0;
+ if (arm->arm_vfp_version == ARM_VFP_V3) {
+ unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
+ for (i = 0; i < 33; i++)
+ (*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
+ }
+
return ERROR_OK;
- break;
default:
LOG_ERROR("not a valid register class type in query.");
return ERROR_FAIL;
- break;
}
}
/* wait for execution to complete and check exit point */
static int armv4_5_run_algorithm_completion(struct target *target,
uint32_t exit_point,
- int timeout_ms,
+ unsigned int timeout_ms,
void *arch_info)
{
int retval;
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info,
+ unsigned int timeout_ms, void *arch_info,
int (*run_it)(struct target *target, uint32_t exit_point,
- int timeout_ms, void *arch_info))
+ unsigned int timeout_ms, void *arch_info))
{
struct arm *arm = target_to_arm(target);
struct arm_algorithm *arm_algorithm_info = arch_info;
}
if (target->state != TARGET_HALTED) {
- LOG_WARNING("target not halted");
+ LOG_TARGET_ERROR(target, "not halted (run target algo)");
return ERROR_TARGET_NOT_HALTED;
}
}
/* armv5 and later can terminate with BKPT instruction; less overhead */
- if (!exit_point && arm->is_armv4) {
+ if (!exit_point && arm->arch == ARM_ARCH_V4) {
LOG_ERROR("ARMv4 target needs HW breakpoint location");
return ERROR_FAIL;
}
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction == PARAM_IN)
+ continue;
retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
mem_params[i].value);
if (retval != ERROR_OK)
}
for (i = 0; i < num_reg_params; i++) {
- struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
+ if (reg_params[i].direction == PARAM_IN)
+ continue;
+
+ struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
arm_algorithm_info->core_mode);
buf_set_u32(arm->cpsr->value, 0, 5,
arm_algorithm_info->core_mode);
- arm->cpsr->dirty = 1;
- arm->cpsr->valid = 1;
+ arm->cpsr->dirty = true;
+ arm->cpsr->valid = true;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
struct reg *reg = register_get_by_name(arm->core_cache,
reg_params[i].reg_name,
- 0);
+ false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
- i).valid = 1;
+ i).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
- i).dirty = 1;
+ i).dirty = true;
}
}
arm_set_cpsr(arm, cpsr);
- arm->cpsr->dirty = 1;
+ arm->cpsr->dirty = true;
arm->core_state = core_state;
struct mem_param *mem_params,
int num_reg_params,
struct reg_param *reg_params,
- uint32_t entry_point,
- uint32_t exit_point,
- int timeout_ms,
+ target_addr_t entry_point,
+ target_addr_t exit_point,
+ unsigned int timeout_ms,
void *arch_info)
{
return armv4_5_run_algorithm_inner(target,
mem_params,
num_reg_params,
reg_params,
- entry_point,
- exit_point,
+ (uint32_t)entry_point,
+ (uint32_t)exit_point,
timeout_ms,
arch_info,
armv4_5_run_algorithm_completion);
*
*/
int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum)
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct arm_algorithm arm_algo;
uint32_t i;
uint32_t exit_var = 0;
- /* see contrib/loaders/checksum/armv4_5_crc.s for src */
-
- static const uint32_t arm_crc_code[] = {
- 0xE1A02000, /* mov r2, r0 */
- 0xE3E00000, /* mov r0, #0xffffffff */
- 0xE1A03001, /* mov r3, r1 */
- 0xE3A04000, /* mov r4, #0 */
- 0xEA00000B, /* b ncomp */
- /* nbyte: */
- 0xE7D21004, /* ldrb r1, [r2, r4] */
- 0xE59F7030, /* ldr r7, CRC32XOR */
- 0xE0200C01, /* eor r0, r0, r1, asl 24 */
- 0xE3A05000, /* mov r5, #0 */
- /* loop: */
- 0xE3500000, /* cmp r0, #0 */
- 0xE1A06080, /* mov r6, r0, asl #1 */
- 0xE2855001, /* add r5, r5, #1 */
- 0xE1A00006, /* mov r0, r6 */
- 0xB0260007, /* eorlt r0, r6, r7 */
- 0xE3550008, /* cmp r5, #8 */
- 0x1AFFFFF8, /* bne loop */
- 0xE2844001, /* add r4, r4, #1 */
- /* ncomp: */
- 0xE1540003, /* cmp r4, r3 */
- 0x1AFFFFF1, /* bne nbyte */
- /* end: */
- 0xe1200070, /* bkpt #0 */
- /* CRC32XOR: */
- 0x04C11DB7 /* .word 0x04C11DB7 */
+ static const uint8_t arm_crc_code_le[] = {
+#include "../../contrib/loaders/checksum/armv4_5_crc.inc"
};
+ assert(sizeof(arm_crc_code_le) % 4 == 0);
+
retval = target_alloc_working_area(target,
- sizeof(arm_crc_code), &crc_algorithm);
+ sizeof(arm_crc_code_le), &crc_algorithm);
if (retval != ERROR_OK)
return retval;
/* convert code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
+ for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
retval = target_write_u32(target,
crc_algorithm->address + i * sizeof(uint32_t),
- arm_crc_code[i]);
+ le_to_h_u32(&arm_crc_code_le[i * 4]));
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
buf_set_u32(reg_params[1].value, 0, 32, count);
/* 20 second timeout/megabyte */
- int timeout = 20000 * (1 + (count / (1024 * 1024)));
+ unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
- exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
+ if (arm->arch == ARM_ARCH_V4)
+ exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
exit_var,
timeout, &arm_algo);
- if (retval != ERROR_OK) {
- LOG_ERROR("error executing ARM crc algorithm");
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- target_free_working_area(target, crc_algorithm);
- return retval;
- }
- *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ if (retval == ERROR_OK)
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ else
+ LOG_ERROR("error executing ARM crc algorithm");
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
+cleanup:
target_free_working_area(target, crc_algorithm);
- return ERROR_OK;
+ return retval;
}
/**
*
*/
int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank)
+ struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
{
struct working_area *check_algorithm;
struct reg_param reg_params[3];
uint32_t i;
uint32_t exit_var = 0;
- /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
-
- static const uint32_t check_code[] = {
- /* loop: */
- 0xe4d03001, /* ldrb r3, [r0], #1 */
- 0xe0022003, /* and r2, r2, r3 */
- 0xe2511001, /* subs r1, r1, #1 */
- 0x1afffffb, /* bne loop */
- /* end: */
- 0xe1200070, /* bkpt #0 */
+ static const uint8_t check_code_le[] = {
+#include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
};
+ assert(sizeof(check_code_le) % 4 == 0);
+
+ if (erased_value != 0xff) {
+ LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
+ erased_value);
+ return ERROR_FAIL;
+ }
+
/* make sure we have a working area */
retval = target_alloc_working_area(target,
- sizeof(check_code), &check_algorithm);
+ sizeof(check_code_le), &check_algorithm);
if (retval != ERROR_OK)
return retval;
/* convert code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(check_code); i++) {
+ for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
retval = target_write_u32(target,
check_algorithm->address
+ i * sizeof(uint32_t),
- check_code[i]);
+ le_to_h_u32(&check_code_le[i * 4]));
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
- buf_set_u32(reg_params[0].value, 0, 32, address);
+ buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
- buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
- buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+ buf_set_u32(reg_params[2].value, 0, 32, erased_value);
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
- exit_var = check_algorithm->address + sizeof(check_code) - 4;
+ if (arm->arch == ARM_ARCH_V4)
+ exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
check_algorithm->address,
exit_var,
10000, &arm_algo);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- target_free_working_area(target, check_algorithm);
- return retval;
- }
- *blank = buf_get_u32(reg_params[2].value, 0, 32);
+ if (retval == ERROR_OK)
+ blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+cleanup:
target_free_working_area(target, check_algorithm);
- return ERROR_OK;
+ if (retval != ERROR_OK)
+ return retval;
+
+ return 1; /* only one block has been checked */
}
static int arm_full_context(struct target *target)
int retval = ERROR_OK;
for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
- if (reg->valid)
+ if (!reg->exist || reg->valid)
continue;
retval = armv4_5_get_core_reg(reg);
}
static int arm_default_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t *value)
{
LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
return ERROR_FAIL;
}
+static int arm_default_mrrc(struct target *target, int cpnum,
+ uint32_t op, uint32_t crm,
+ uint64_t *value)
+{
+ LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+ return ERROR_FAIL;
+}
+
static int arm_default_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t value)
{
LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
return ERROR_FAIL;
}
+static int arm_default_mcrr(struct target *target, int cpnum,
+ uint32_t op, uint32_t crm,
+ uint64_t value)
+{
+ LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+ return ERROR_FAIL;
+}
+
int arm_init_arch_info(struct target *target, struct arm *arm)
{
target->arch_info = arm;
arm->common_magic = ARM_COMMON_MAGIC;
/* core_type may be overridden by subtype logic */
- if (arm->core_type != ARM_MODE_THREAD) {
- arm->core_type = ARM_MODE_ANY;
+ if (arm->core_type != ARM_CORE_TYPE_M_PROFILE) {
+ arm->core_type = ARM_CORE_TYPE_STD;
arm_set_cpsr(arm, ARM_MODE_USR);
}
if (!arm->mrc)
arm->mrc = arm_default_mrc;
+ if (!arm->mrrc)
+ arm->mrrc = arm_default_mrrc;
if (!arm->mcr)
arm->mcr = arm_default_mcr;
+ if (!arm->mcrr)
+ arm->mcrr = arm_default_mcrr;
return ERROR_OK;
}
Code Review / openocd.git / blobdiff