+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Copyright (C) 2005 by Dominic Rath
* Dominic.Rath@gmx.de
*
* Copyright (C) 2009 by Øyvind Harboe
* oyvind.harboe@zylin.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef __ARM_OPCODES_H
-#define __ARM_OPCODES_H
+
+#ifndef OPENOCD_TARGET_ARM_OPCODES_H
+#define OPENOCD_TARGET_ARM_OPCODES_H
/**
* @file
/* ARM mode instructions */
/* Store multiple increment after
- * Rn: base register
- * List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
- * W = 1: update the base register. W = 0: leave the base register untouched
+ * rn: base register
+ * list: for each bit in list: store register
+ * s: in privileged mode: store user-mode registers
+ * w = 1: update the base register. w = 0: leave the base register untouched
*/
-#define ARMV4_5_STMIA(Rn, List, S, W) \
- (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+#define ARMV4_5_STMIA(rn, list, s, w) \
+ (0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
/* Load multiple increment after
- * Rn: base register
- * List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
- * W = 1: update the base register. W = 0: leave the base register untouched
+ * rn: base register
+ * list: for each bit in list: store register
+ * s: in privileged mode: store user-mode registers
+ * w = 1: update the base register. w = 0: leave the base register untouched
*/
-#define ARMV4_5_LDMIA(Rn, List, S, W) \
- (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+#define ARMV4_5_LDMIA(rn, list, s, w) \
+ (0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
/* MOV r8, r8 */
#define ARMV4_5_NOP (0xe1a08008)
/* Move PSR to general purpose register
- * R = 1: SPSR R = 0: CPSR
- * Rn: target register
+ * r = 1: SPSR r = 0: CPSR
+ * rn: target register
*/
-#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
+#define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
/* Store register
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
*/
-#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
/* Load register
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
*/
-#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
/* Move general purpose register to PSR
- * R = 1: SPSR R = 0: CPSR
- * Field: Field mask
+ * r = 1: SPSR r = 0: CPSR
+ * field: Field mask
* 1: control field 2: extension field 4: status field 8: flags field
- * Rm: source register
+ * rm: source register
*/
-#define ARMV4_5_MSR_GP(Rm, Field, R) \
- (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
-#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
- (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+#define ARMV4_5_MSR_GP(rm, field, r) \
+ (0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
+#define ARMV4_5_MSR_IM(im, rotate, field, r) \
+ (0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
/* Load Register Word Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
*/
-#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
/* Load Register Halfword Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
*/
-#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
/* Load Register Byte Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
*/
-#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
/* Store register Word Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
*/
-#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
/* Store register Halfword Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
*/
-#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
/* Store register Byte Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
*/
-#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
/* Branch (and Link)
- * Im: Branch target (left-shifted by 2 bits, added to PC)
- * L: 1: branch and link 0: branch only
+ * im: Branch target (left-shifted by 2 bits, added to PC)
+ * l: 1: branch and link 0: branch only
*/
-#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
+#define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
/* Branch and exchange (ARM state)
- * Rm: register holding branch target address
+ * rm: register holding branch target address
+ */
+#define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
+
+/* Copies two words from two ARM core registers
+ * into a doubleword extension register, or
+ * from a doubleword extension register to two ARM core registers.
+ * See Armv7-A arch reference manual section A8.8.345
+ * rt: Arm core register 1
+ * rt2: Arm core register 2
+ * vm: The doubleword extension register
+ * m: m = UInt(m:vm);
+ * op: to_arm_registers = (op == ‘1’);
*/
-#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
+#define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
+ (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
+ ((rt) << 12) | ((m) << 5) | (vm))
+
+/* Moves the value of the FPSCR to an ARM core register
+ * rt: Arm core register
+ */
+#define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
+
+/* Moves the value of an ARM core register to the FPSCR.
+ * rt: Arm core register
+ */
+#define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
/* Store data from coprocessor to consecutive memory
* See Armv7-A arch doc section A8.6.187
- * P: 1=index mode (offset from Rn)
- * U: 1=add, 0=subtract Rn address with imm
- * D: Opcode D encoding
- * W: write back the offset start address to the Rn register
- * CP: Coprocessor number (4 bits)
- * CRd: Coprocessor source register (4 bits)
- * Rn: Base register for memory address (4 bits)
+ * p: 1=index mode (offset from rn)
+ * u: 1=add, 0=subtract rn address with imm
+ * d: Opcode D encoding
+ * w: write back the offset start address to the rn register
+ * cp: Coprocessor number (4 bits)
+ * crd: Coprocessor source register (4 bits)
+ * rn: Base register for memory address (4 bits)
* imm: Immediate value (0 - 1020, must be divisible by 4)
*/
-#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
- (0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
- ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
+#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
+ (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+ ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
/* Loads data from consecutive memory to coprocessor
* See Armv7-A arch doc section A8.6.51
- * P: 1=index mode (offset from Rn)
- * U: 1=add, 0=subtract Rn address with imm
- * D: Opcode D encoding
- * W: write back the offset start address to the Rn register
- * CP: Coprocessor number (4 bits)
- * CRd: Coprocessor dest register (4 bits)
- * Rn: Base register for memory address (4 bits)
+ * p: 1=index mode (offset from rn)
+ * u: 1=add, 0=subtract rn address with imm
+ * d: Opcode D encoding
+ * w: write back the offset start address to the rn register
+ * cp: Coprocessor number (4 bits)
+ * crd: Coprocessor dest register (4 bits)
+ * rn: Base register for memory address (4 bits)
* imm: Immediate value (0 - 1020, must be divisible by 4)
*/
-#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
- (0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
- ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
+#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
+ (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+ ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
/* Move to ARM register from coprocessor
- * CP: Coprocessor number
+ * cp: Coprocessor number
* op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
+ * rd: destination register
+ * crn: first coprocessor operand
+ * crm: second coprocessor operand
* op2: Second coprocessor opcode
*/
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
- (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
- | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
+ (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
+ | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
+
+/* Move to two ARM registers from coprocessor
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
+ (0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
+ | ((rt) << 12) | ((rt2) << 16))
/* Move to coprocessor from ARM register
- * CP: Coprocessor number
+ * cp: Coprocessor number
* op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
+ * rd: destination register
+ * crn: first coprocessor operand
+ * crm: second coprocessor operand
* op2: Second coprocessor opcode
*/
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
- (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
- | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
+ (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
+ | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
+
+/* Move to coprocessor from two ARM registers
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
+ (0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
+ | ((rt) << 12) | ((rt2) << 16))
/* Breakpoint instruction (ARMv5)
- * Im: 16-bit immediate
+ * im: 16-bit immediate
*/
-#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
+#define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
/* Thumb mode instructions
*/
/* Store register (Thumb mode)
- * Rd: source register
- * Rn: base register
+ * rd: source register
+ * rn: base register
*/
-#define ARMV4_5_T_STR(Rd, Rn) \
- ((0x6000 | (Rd) | ((Rn) << 3)) | \
- ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
+#define ARMV4_5_T_STR(rd, rn) \
+ ((0x6000 | (rd) | ((rn) << 3)) | \
+ ((0x6000 | (rd) | ((rn) << 3)) << 16))
/* Load register (Thumb state)
- * Rd: destination register
- * Rn: base register
+ * rd: destination register
+ * rn: base register
*/
-#define ARMV4_5_T_LDR(Rd, Rn) \
- ((0x6800 | ((Rn) << 3) | (Rd)) \
- | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
+#define ARMV4_5_T_LDR(rd, rn) \
+ ((0x6800 | ((rn) << 3) | (rd)) \
+ | ((0x6800 | ((rn) << 3) | (rd)) << 16))
/* Load multiple (Thumb state)
- * Rn: base register
- * List: for each bit in list: store register
+ * rn: base register
+ * list: for each bit in list: store register
*/
-#define ARMV4_5_T_LDMIA(Rn, List) \
- ((0xc800 | ((Rn) << 8) | (List)) \
- | ((0xc800 | ((Rn) << 8) | (List)) << 16))
+#define ARMV4_5_T_LDMIA(rn, list) \
+ ((0xc800 | ((rn) << 8) | (list)) \
+ | ((0xc800 | ((rn) << 8) | (list)) << 16))
/* Load register with PC relative addressing
- * Rd: register to load
+ * rd: register to load
*/
-#define ARMV4_5_T_LDR_PCREL(Rd) \
- ((0x4800 | ((Rd) << 8)) \
- | ((0x4800 | ((Rd) << 8)) << 16))
+#define ARMV4_5_T_LDR_PCREL(rd) \
+ ((0x4800 | ((rd) << 8)) \
+ | ((0x4800 | ((rd) << 8)) << 16))
/* Move hi register (Thumb mode)
- * Rd: destination register
- * Rm: source register
+ * rd: destination register
+ * rm: source register
*/
-#define ARMV4_5_T_MOV(Rd, Rm) \
- ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
- (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
- | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
- (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
+#define ARMV4_5_T_MOV(rd, rm) \
+ ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
+ (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
+ | ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
+ (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
/* No operation (Thumb mode)
* NOTE: this is "MOV r8, r8" ... Thumb2 adds two
#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
/* Move immediate to register (Thumb state)
- * Rd: destination register
- * Im: 8-bit immediate value
+ * rd: destination register
+ * im: 8-bit immediate value
*/
-#define ARMV4_5_T_MOV_IM(Rd, Im) \
- ((0x2000 | ((Rd) << 8) | (Im)) \
- | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
+#define ARMV4_5_T_MOV_IM(rd, im) \
+ ((0x2000 | ((rd) << 8) | (im)) \
+ | ((0x2000 | ((rd) << 8) | (im)) << 16))
/* Branch and Exchange
- * Rm: register containing branch target
+ * rm: register containing branch target
*/
-#define ARMV4_5_T_BX(Rm) \
- ((0x4700 | ((Rm) << 3)) \
- | ((0x4700 | ((Rm) << 3)) << 16))
+#define ARMV4_5_T_BX(rm) \
+ ((0x4700 | ((rm) << 3)) \
+ | ((0x4700 | ((rm) << 3)) << 16))
/* Branch (Thumb state)
- * Imm: Branch target
+ * imm: Branch target
*/
-#define ARMV4_5_T_B(Imm) \
- ((0xe000 | (Imm)) \
- | ((0xe000 | (Imm)) << 16))
+#define ARMV4_5_T_B(imm) \
+ ((0xe000 | (imm)) \
+ | ((0xe000 | (imm)) << 16))
/* Breakpoint instruction (ARMv5) (Thumb state)
* Im: 8-bit immediate
*/
-#define ARMV5_T_BKPT(Im) \
- ((0xbe00 | (Im)) \
- | ((0xbe00 | (Im)) << 16))
+#define ARMV5_T_BKPT(im) \
+ ((0xbe00 | (im)) \
+ | ((0xbe00 | (im)) << 16))
/* Move to Register from Special Register
* 32 bit Thumb2 instruction
- * Rd: destination register
- * SYSm: source special register
+ * rd: destination register
+ * sysm: source special register
*/
-#define ARM_T2_MRS(Rd, SYSm) \
- ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
+#define ARM_T2_MRS(rd, sysm) \
+ ((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
/* Move from Register from Special Register
* 32 bit Thumb2 instruction
- * Rd: source register
- * SYSm: destination special register
+ * rd: source register
+ * sysm: destination special register
*/
-#define ARM_T2_MSR(SYSm, Rn) \
- ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
+#define ARM_T2_MSR(sysm, rn) \
+ ((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
/* Change Processor State.
* 16 bit Thumb2 instruction
- * Rd: source register
+ * rd: source register
* IF: A_FLAG and/or I_FLAG and/or F_FLAG
*/
#define A_FLAG 4
#define I_FLAG 2
#define F_FLAG 1
-#define ARM_T2_CPSID(IF) \
- ((0xB660 | (1 << 8) | ((IF)&0x3)) \
- | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
-#define ARM_T2_CPSIE(IF) \
- ((0xB660 | (0 << 8) | ((IF)&0x3)) \
- | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
-
-#endif /* __ARM_OPCODES_H */
+#define ARM_T2_CPSID(_if) \
+ ((0xB660 | (1 << 8) | ((_if)&0x3)) \
+ | ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
+#define ARM_T2_CPSIE(_if) \
+ ((0xB660 | (0 << 8) | ((_if)&0x3)) \
+ | ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
+
+#endif /* OPENOCD_TARGET_ARM_OPCODES_H */
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