+
+ LOG_ERROR("ARM: should never reach this point (opcode=%08x)",
+ (unsigned) opcode);
+ return -1;
+}
+
+static int evaluate_b_bl_blx_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t offset = opcode & 0x7ff;
+ uint32_t opc = (opcode >> 11) & 0x3;
+ uint32_t target_address;
+ char *mnemonic = NULL;
+
+ /* sign extend 11-bit offset */
+ if (((opc == 0) || (opc == 2)) && (offset & 0x00000400))
+ offset = 0xfffff800 | offset;
+
+ target_address = address + 4 + (offset << 1);
+
+ switch (opc) {
+ /* unconditional branch */
+ case 0:
+ instruction->type = ARM_B;
+ mnemonic = "B";
+ break;
+ /* BLX suffix */
+ case 1:
+ instruction->type = ARM_BLX;
+ mnemonic = "BLX";
+ target_address &= 0xfffffffc;
+ break;
+ /* BL/BLX prefix */
+ case 2:
+ instruction->type = ARM_UNKNOWN_INSTRUCTION;
+ mnemonic = "prefix";
+ target_address = offset << 12;
+ break;
+ /* BL suffix */
+ case 3:
+ instruction->type = ARM_BL;
+ mnemonic = "BL";
+ break;
+ }
+
+ /* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
+ * these are effectively 32-bit instructions even in Thumb1. For
+ * disassembly, it's simplest to always use the Thumb2 decoder.
+ *
+ * But some cores will evidently handle them as two instructions,
+ * where exceptions may occur between the two. The ETMv3.2+ ID
+ * register has a bit which exposes this behavior.
+ */
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\t%#8.8" PRIx32,
+ address, opcode, mnemonic, target_address);
+
+ instruction->info.b_bl_bx_blx.reg_operand = -1;
+ instruction->info.b_bl_bx_blx.target_address = target_address;
+
+ return ERROR_OK;
+}
+
+static int evaluate_add_sub_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint8_t rd = (opcode >> 0) & 0x7;
+ uint8_t rn = (opcode >> 3) & 0x7;
+ uint8_t rm_imm = (opcode >> 6) & 0x7;
+ uint32_t opc = opcode & (1 << 9);
+ uint32_t reg_imm = opcode & (1 << 10);
+ char *mnemonic;
+
+ if (opc) {
+ instruction->type = ARM_SUB;
+ mnemonic = "SUBS";
+ } else {
+ /* REVISIT: if reg_imm == 0, display as "MOVS" */
+ instruction->type = ARM_ADD;
+ mnemonic = "ADDS";
+ }
+
+ instruction->info.data_proc.rd = rd;
+ instruction->info.data_proc.rn = rn;
+ instruction->info.data_proc.s = 1;
+
+ if (reg_imm) {
+ instruction->info.data_proc.variant = 0;/*immediate*/
+ instruction->info.data_proc.shifter_operand.immediate.immediate = rm_imm;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d",
+ address, opcode, mnemonic, rd, rn, rm_imm);
+ } else {
+ instruction->info.data_proc.variant = 1;/*immediate shift*/
+ instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm_imm;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i",
+ address, opcode, mnemonic, rd, rn, rm_imm);
+ }
+
+ return ERROR_OK;
+}
+
+static int evaluate_shift_imm_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint8_t rd = (opcode >> 0) & 0x7;
+ uint8_t rm = (opcode >> 3) & 0x7;
+ uint8_t imm = (opcode >> 6) & 0x1f;
+ uint8_t opc = (opcode >> 11) & 0x3;
+ char *mnemonic = NULL;
+
+ switch (opc) {
+ case 0:
+ instruction->type = ARM_MOV;
+ mnemonic = "LSLS";
+ instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0;
+ break;
+ case 1:
+ instruction->type = ARM_MOV;
+ mnemonic = "LSRS";
+ instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1;
+ break;
+ case 2:
+ instruction->type = ARM_MOV;
+ mnemonic = "ASRS";
+ instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2;
+ break;
+ }
+
+ if ((imm == 0) && (opc != 0))
+ imm = 32;
+
+ instruction->info.data_proc.rd = rd;
+ instruction->info.data_proc.rn = -1;
+ instruction->info.data_proc.s = 1;
+
+ instruction->info.data_proc.variant = 1;/*immediate_shift*/
+ instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
+ instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%#2.2x",
+ address, opcode, mnemonic, rd, rm, imm);
+
+ return ERROR_OK;
+}
+
+static int evaluate_data_proc_imm_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint8_t imm = opcode & 0xff;
+ uint8_t rd = (opcode >> 8) & 0x7;
+ uint32_t opc = (opcode >> 11) & 0x3;
+ char *mnemonic = NULL;
+
+ instruction->info.data_proc.rd = rd;
+ instruction->info.data_proc.rn = rd;
+ instruction->info.data_proc.s = 1;
+ instruction->info.data_proc.variant = 0;/*immediate*/
+ instruction->info.data_proc.shifter_operand.immediate.immediate = imm;
+
+ switch (opc) {
+ case 0:
+ instruction->type = ARM_MOV;
+ mnemonic = "MOVS";
+ instruction->info.data_proc.rn = -1;
+ break;
+ case 1:
+ instruction->type = ARM_CMP;
+ mnemonic = "CMP";
+ instruction->info.data_proc.rd = -1;
+ break;
+ case 2:
+ instruction->type = ARM_ADD;
+ mnemonic = "ADDS";
+ break;
+ case 3:
+ instruction->type = ARM_SUB;
+ mnemonic = "SUBS";
+ break;
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, #%#2.2x",
+ address, opcode, mnemonic, rd, imm);
+
+ return ERROR_OK;
+}
+
+static int evaluate_data_proc_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint8_t high_reg, op, rm, rd, h1, h2;
+ char *mnemonic = NULL;
+ bool nop = false;
+
+ high_reg = (opcode & 0x0400) >> 10;
+ op = (opcode & 0x03C0) >> 6;
+
+ rd = (opcode & 0x0007);
+ rm = (opcode & 0x0038) >> 3;
+ h1 = (opcode & 0x0080) >> 7;
+ h2 = (opcode & 0x0040) >> 6;
+
+ instruction->info.data_proc.rd = rd;
+ instruction->info.data_proc.rn = rd;
+ instruction->info.data_proc.s = (!high_reg || (instruction->type == ARM_CMP));
+ instruction->info.data_proc.variant = 1 /*immediate shift*/;
+ instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
+
+ if (high_reg) {
+ rd |= h1 << 3;
+ rm |= h2 << 3;
+ op >>= 2;
+
+ switch (op) {
+ case 0x0:
+ instruction->type = ARM_ADD;
+ mnemonic = "ADD";
+ break;
+ case 0x1:
+ instruction->type = ARM_CMP;
+ mnemonic = "CMP";
+ break;
+ case 0x2:
+ instruction->type = ARM_MOV;
+ mnemonic = "MOV";
+ if (rd == rm)
+ nop = true;
+ break;
+ case 0x3:
+ if ((opcode & 0x7) == 0x0) {
+ instruction->info.b_bl_bx_blx.reg_operand = rm;
+ if (h1) {
+ instruction->type = ARM_BLX;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \tBLX\tr%i",
+ address, opcode, rm);
+ } else {
+ instruction->type = ARM_BX;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \tBX\tr%i",
+ address, opcode, rm);
+ }
+ } else {
+ instruction->type = ARM_UNDEFINED_INSTRUCTION;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \t"
+ "UNDEFINED INSTRUCTION",
+ address, opcode);
+ }
+ return ERROR_OK;
+ }
+ } else {
+ switch (op) {
+ case 0x0:
+ instruction->type = ARM_AND;
+ mnemonic = "ANDS";
+ break;
+ case 0x1:
+ instruction->type = ARM_EOR;
+ mnemonic = "EORS";
+ break;
+ case 0x2:
+ instruction->type = ARM_MOV;
+ mnemonic = "LSLS";
+ instruction->info.data_proc.variant = 2 /*register shift*/;
+ instruction->info.data_proc.shifter_operand.register_shift.shift = 0;
+ instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+ instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
+ break;
+ case 0x3:
+ instruction->type = ARM_MOV;
+ mnemonic = "LSRS";
+ instruction->info.data_proc.variant = 2 /*register shift*/;
+ instruction->info.data_proc.shifter_operand.register_shift.shift = 1;
+ instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+ instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
+ break;
+ case 0x4:
+ instruction->type = ARM_MOV;
+ mnemonic = "ASRS";
+ instruction->info.data_proc.variant = 2 /*register shift*/;
+ instruction->info.data_proc.shifter_operand.register_shift.shift = 2;
+ instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+ instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
+ break;
+ case 0x5:
+ instruction->type = ARM_ADC;
+ mnemonic = "ADCS";
+ break;
+ case 0x6:
+ instruction->type = ARM_SBC;
+ mnemonic = "SBCS";
+ break;
+ case 0x7:
+ instruction->type = ARM_MOV;
+ mnemonic = "RORS";
+ instruction->info.data_proc.variant = 2 /*register shift*/;
+ instruction->info.data_proc.shifter_operand.register_shift.shift = 3;
+ instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+ instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
+ break;
+ case 0x8:
+ instruction->type = ARM_TST;
+ mnemonic = "TST";
+ break;
+ case 0x9:
+ instruction->type = ARM_RSB;
+ mnemonic = "RSBS";
+ instruction->info.data_proc.variant = 0 /*immediate*/;
+ instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
+ instruction->info.data_proc.rn = rm;
+ break;
+ case 0xA:
+ instruction->type = ARM_CMP;
+ mnemonic = "CMP";
+ break;
+ case 0xB:
+ instruction->type = ARM_CMN;
+ mnemonic = "CMN";
+ break;
+ case 0xC:
+ instruction->type = ARM_ORR;
+ mnemonic = "ORRS";
+ break;
+ case 0xD:
+ instruction->type = ARM_MUL;
+ mnemonic = "MULS";
+ break;
+ case 0xE:
+ instruction->type = ARM_BIC;
+ mnemonic = "BICS";
+ break;
+ case 0xF:
+ instruction->type = ARM_MVN;
+ mnemonic = "MVNS";
+ break;
+ }
+ }
+
+ if (nop)
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tNOP\t\t\t"
+ "; (%s r%i, r%i)",
+ address, opcode, mnemonic, rd, rm);
+ else
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i",
+ address, opcode, mnemonic, rd, rm);
+
+ return ERROR_OK;
+}
+
+/* PC-relative data addressing is word-aligned even with Thumb */
+static inline uint32_t thumb_alignpc4(uint32_t addr)
+{
+ return (addr + 4) & ~3;
+}
+
+static int evaluate_load_literal_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t immediate;
+ uint8_t rd = (opcode >> 8) & 0x7;
+
+ instruction->type = ARM_LDR;
+ immediate = opcode & 0x000000ff;
+ immediate *= 4;
+
+ instruction->info.load_store.rd = rd;
+ instruction->info.load_store.rn = 15 /*PC*/;
+ instruction->info.load_store.index_mode = 0; /*offset*/
+ instruction->info.load_store.offset_mode = 0; /*immediate*/
+ instruction->info.load_store.offset.offset = immediate;
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t"
+ "LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32,
+ address, opcode, rd, immediate,
+ thumb_alignpc4(address) + immediate);
+
+ return ERROR_OK;
+}
+
+static int evaluate_load_store_reg_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint8_t rd = (opcode >> 0) & 0x7;
+ uint8_t rn = (opcode >> 3) & 0x7;
+ uint8_t rm = (opcode >> 6) & 0x7;
+ uint8_t opc = (opcode >> 9) & 0x7;
+ char *mnemonic = NULL;
+
+ switch (opc) {
+ case 0:
+ instruction->type = ARM_STR;
+ mnemonic = "STR";
+ break;
+ case 1:
+ instruction->type = ARM_STRH;
+ mnemonic = "STRH";
+ break;
+ case 2:
+ instruction->type = ARM_STRB;
+ mnemonic = "STRB";
+ break;
+ case 3:
+ instruction->type = ARM_LDRSB;
+ mnemonic = "LDRSB";
+ break;
+ case 4:
+ instruction->type = ARM_LDR;
+ mnemonic = "LDR";
+ break;
+ case 5:
+ instruction->type = ARM_LDRH;
+ mnemonic = "LDRH";
+ break;
+ case 6:
+ instruction->type = ARM_LDRB;
+ mnemonic = "LDRB";
+ break;
+ case 7:
+ instruction->type = ARM_LDRSH;
+ mnemonic = "LDRSH";
+ break;
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [r%i, r%i]",
+ address, opcode, mnemonic, rd, rn, rm);
+
+ instruction->info.load_store.rd = rd;
+ instruction->info.load_store.rn = rn;
+ instruction->info.load_store.index_mode = 0; /*offset*/
+ instruction->info.load_store.offset_mode = 1; /*register*/
+ instruction->info.load_store.offset.reg.rm = rm;
+
+ return ERROR_OK;
+}
+
+static int evaluate_load_store_imm_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t offset = (opcode >> 6) & 0x1f;
+ uint8_t rd = (opcode >> 0) & 0x7;
+ uint8_t rn = (opcode >> 3) & 0x7;
+ uint32_t l = opcode & (1 << 11);
+ uint32_t b = opcode & (1 << 12);
+ char *mnemonic;
+ char suffix = ' ';
+ uint32_t shift = 2;
+
+ if (l) {
+ instruction->type = ARM_LDR;
+ mnemonic = "LDR";
+ } else {
+ instruction->type = ARM_STR;
+ mnemonic = "STR";
+ }
+
+ if ((opcode&0xF000) == 0x8000) {
+ suffix = 'H';
+ shift = 1;
+ } else if (b) {
+ suffix = 'B';
+ shift = 0;
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s%c\tr%i, [r%i, #%#" PRIx32 "]",
+ address, opcode, mnemonic, suffix, rd, rn, offset << shift);
+
+ instruction->info.load_store.rd = rd;
+ instruction->info.load_store.rn = rn;
+ instruction->info.load_store.index_mode = 0; /*offset*/
+ instruction->info.load_store.offset_mode = 0; /*immediate*/
+ instruction->info.load_store.offset.offset = offset << shift;
+
+ return ERROR_OK;
+}
+
+static int evaluate_load_store_stack_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t offset = opcode & 0xff;
+ uint8_t rd = (opcode >> 8) & 0x7;
+ uint32_t l = opcode & (1 << 11);
+ char *mnemonic;
+
+ if (l) {
+ instruction->type = ARM_LDR;
+ mnemonic = "LDR";
+ } else {
+ instruction->type = ARM_STR;
+ mnemonic = "STR";
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [SP, #%#" PRIx32 "]",
+ address, opcode, mnemonic, rd, offset*4);
+
+ instruction->info.load_store.rd = rd;
+ instruction->info.load_store.rn = 13 /*SP*/;
+ instruction->info.load_store.index_mode = 0; /*offset*/
+ instruction->info.load_store.offset_mode = 0; /*immediate*/
+ instruction->info.load_store.offset.offset = offset*4;
+
+ return ERROR_OK;
+}
+
+static int evaluate_add_sp_pc_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t imm = opcode & 0xff;
+ uint8_t rd = (opcode >> 8) & 0x7;
+ uint8_t rn;
+ uint32_t sp = opcode & (1 << 11);
+ const char *reg_name;
+
+ instruction->type = ARM_ADD;
+
+ if (sp) {
+ reg_name = "SP";
+ rn = 13;
+ } else {
+ reg_name = "PC";
+ rn = 15;
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tADD\tr%i, %s, #%#" PRIx32,
+ address, opcode, rd, reg_name, imm * 4);
+
+ instruction->info.data_proc.variant = 0 /* immediate */;
+ instruction->info.data_proc.rd = rd;
+ instruction->info.data_proc.rn = rn;
+ instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
+
+ return ERROR_OK;
+}
+
+static int evaluate_adjust_stack_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t imm = opcode & 0x7f;
+ uint8_t opc = opcode & (1 << 7);
+ char *mnemonic;
+
+
+ if (opc) {
+ instruction->type = ARM_SUB;
+ mnemonic = "SUB";
+ } else {
+ instruction->type = ARM_ADD;
+ mnemonic = "ADD";
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tSP, #%#" PRIx32,
+ address, opcode, mnemonic, imm*4);
+
+ instruction->info.data_proc.variant = 0 /* immediate */;
+ instruction->info.data_proc.rd = 13 /*SP*/;
+ instruction->info.data_proc.rn = 13 /*SP*/;
+ instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
+
+ return ERROR_OK;
+}
+
+static int evaluate_breakpoint_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t imm = opcode & 0xff;
+
+ instruction->type = ARM_BKPT;
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32 "",
+ address, opcode, imm);
+
+ return ERROR_OK;
+}
+
+static int evaluate_load_store_multiple_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t reg_list = opcode & 0xff;
+ uint32_t l = opcode & (1 << 11);
+ uint32_t r = opcode & (1 << 8);
+ uint8_t rn = (opcode >> 8) & 7;
+ uint8_t addr_mode = 0 /* IA */;
+ char reg_names[40];
+ char *reg_names_p;
+ char *mnemonic;
+ char ptr_name[7] = "";
+ int i;
+
+ /* REVISIT: in ThumbEE mode, there are no LDM or STM instructions.
+ * The STMIA and LDMIA opcodes are used for other instructions.
+ */
+
+ if ((opcode & 0xf000) == 0xc000) { /* generic load/store multiple */
+ char *wback = "!";
+
+ if (l) {
+ instruction->type = ARM_LDM;
+ mnemonic = "LDM";
+ if (opcode & (1 << rn))
+ wback = "";
+ } else {
+ instruction->type = ARM_STM;
+ mnemonic = "STM";
+ }
+ snprintf(ptr_name, sizeof(ptr_name), "r%i%s, ", rn, wback);
+ } else {/* push/pop */
+ rn = 13;/* SP */
+ if (l) {
+ instruction->type = ARM_LDM;
+ mnemonic = "POP";
+ if (r)
+ reg_list |= (1 << 15) /*PC*/;
+ } else {
+ instruction->type = ARM_STM;
+ mnemonic = "PUSH";
+ addr_mode = 3; /*DB*/
+ if (r)
+ reg_list |= (1 << 14) /*LR*/;
+ }
+ }
+
+ reg_names_p = reg_names;
+ for (i = 0; i <= 15; i++) {
+ if (reg_list & (1 << i))
+ reg_names_p += snprintf(reg_names_p,
+ (reg_names + 40 - reg_names_p),
+ "r%i, ",
+ i);
+ }
+ if (reg_names_p > reg_names)
+ reg_names_p[-2] = '\0';
+ else /* invalid op : no registers */
+ reg_names[0] = '\0';
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\t%s{%s}",
+ address, opcode, mnemonic, ptr_name, reg_names);
+
+ instruction->info.load_store_multiple.register_list = reg_list;
+ instruction->info.load_store_multiple.rn = rn;
+ instruction->info.load_store_multiple.addressing_mode = addr_mode;
+
+ return ERROR_OK;
+}
+
+static int evaluate_cond_branch_thumb(uint16_t opcode,
+ uint32_t address, struct arm_instruction *instruction)
+{
+ uint32_t offset = opcode & 0xff;
+ uint8_t cond = (opcode >> 8) & 0xf;
+ uint32_t target_address;
+
+ if (cond == 0xf) {
+ instruction->type = ARM_SWI;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tSVC\t%#2.2" PRIx32,
+ address, opcode, offset);
+ return ERROR_OK;
+ } else if (cond == 0xe) {
+ instruction->type = ARM_UNDEFINED_INSTRUCTION;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
+ address, opcode);
+ return ERROR_OK;
+ }
+
+ /* sign extend 8-bit offset */
+ if (offset & 0x00000080)
+ offset = 0xffffff00 | offset;
+
+ target_address = address + 4 + (offset << 1);
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tB%s\t%#8.8" PRIx32,
+ address, opcode,
+ arm_condition_strings[cond], target_address);
+
+ instruction->type = ARM_B;
+ instruction->info.b_bl_bx_blx.reg_operand = -1;
+ instruction->info.b_bl_bx_blx.target_address = target_address;
+
+ return ERROR_OK;
+}
+
+static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ unsigned offset;
+
+ /* added in Thumb2 */
+ offset = (opcode >> 3) & 0x1f;
+ offset |= (opcode & 0x0200) >> 4;
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tCB%sZ\tr%d, %#8.8" PRIx32,
+ address, opcode,
+ (opcode & 0x0800) ? "N" : "",
+ opcode & 0x7, address + 4 + (offset << 1));
+
+ return ERROR_OK;
+}
+
+static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ /* added in ARMv6 */
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%cXT%c\tr%d, r%d",
+ address, opcode,
+ (opcode & 0x0080) ? 'U' : 'S',
+ (opcode & 0x0040) ? 'B' : 'H',
+ opcode & 0x7, (opcode >> 3) & 0x7);
+
+ return ERROR_OK;
+}
+
+static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ /* added in ARMv6 */
+ if ((opcode & 0x0ff0) == 0x0650)
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tSETEND %s",
+ address, opcode,
+ (opcode & 0x80) ? "BE" : "LE");
+ else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c\t%s%s%s",
+ address, opcode,
+ (opcode & 0x0010) ? 'D' : 'E',
+ (opcode & 0x0004) ? "A" : "",
+ (opcode & 0x0002) ? "I" : "",
+ (opcode & 0x0001) ? "F" : "");
+
+ return ERROR_OK;
+}
+
+static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ char *suffix;
+
+ /* added in ARMv6 */
+ switch ((opcode >> 6) & 3) {
+ case 0:
+ suffix = "";
+ break;
+ case 1:
+ suffix = "16";
+ break;
+ default:
+ suffix = "SH";
+ break;
+ }
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tREV%s\tr%d, r%d",
+ address, opcode, suffix,
+ opcode & 0x7, (opcode >> 3) & 0x7);
+
+ return ERROR_OK;
+}
+
+static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ char *hint;
+
+ switch ((opcode >> 4) & 0x0f) {
+ case 0:
+ hint = "NOP";
+ break;
+ case 1:
+ hint = "YIELD";
+ break;
+ case 2:
+ hint = "WFE";
+ break;
+ case 3:
+ hint = "WFI";
+ break;
+ case 4:
+ hint = "SEV";
+ break;
+ default:
+ hint = "HINT (UNRECOGNIZED)";
+ break;
+ }
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s",
+ address, opcode, hint);
+
+ return ERROR_OK;
+}
+
+static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
+{
+ unsigned cond = (opcode >> 4) & 0x0f;
+ char *x = "", *y = "", *z = "";
+
+ if (opcode & 0x01)
+ z = (opcode & 0x02) ? "T" : "E";
+ if (opcode & 0x03)
+ y = (opcode & 0x04) ? "T" : "E";
+ if (opcode & 0x07)
+ x = (opcode & 0x08) ? "T" : "E";
+
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tIT%s%s%s\t%s",
+ address, opcode,
+ x, y, z, arm_condition_strings[cond]);
+
+ /* NOTE: strictly speaking, the next 1-4 instructions should
+ * now be displayed with the relevant conditional suffix...
+ */
+
+ return ERROR_OK;
+}
+
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruction *instruction)
+{
+ /* clear fields, to avoid confusion */
+ memset(instruction, 0, sizeof(struct arm_instruction));
+ instruction->opcode = opcode;
+ instruction->instruction_size = 2;
+
+ if ((opcode & 0xe000) == 0x0000) {
+ /* add/subtract register or immediate */
+ if ((opcode & 0x1800) == 0x1800)
+ return evaluate_add_sub_thumb(opcode, address, instruction);
+ /* shift by immediate */
+ else
+ return evaluate_shift_imm_thumb(opcode, address, instruction);
+ }
+
+ /* Add/subtract/compare/move immediate */
+ if ((opcode & 0xe000) == 0x2000)
+ return evaluate_data_proc_imm_thumb(opcode, address, instruction);
+
+ /* Data processing instructions */
+ if ((opcode & 0xf800) == 0x4000)
+ return evaluate_data_proc_thumb(opcode, address, instruction);
+
+ /* Load from literal pool */
+ if ((opcode & 0xf800) == 0x4800)
+ return evaluate_load_literal_thumb(opcode, address, instruction);
+
+ /* Load/Store register offset */
+ if ((opcode & 0xf000) == 0x5000)
+ return evaluate_load_store_reg_thumb(opcode, address, instruction);
+
+ /* Load/Store immediate offset */
+ if (((opcode & 0xe000) == 0x6000)
+ || ((opcode & 0xf000) == 0x8000))
+ return evaluate_load_store_imm_thumb(opcode, address, instruction);
+
+ /* Load/Store from/to stack */
+ if ((opcode & 0xf000) == 0x9000)
+ return evaluate_load_store_stack_thumb(opcode, address, instruction);
+
+ /* Add to SP/PC */
+ if ((opcode & 0xf000) == 0xa000)
+ return evaluate_add_sp_pc_thumb(opcode, address, instruction);
+
+ /* Misc */
+ if ((opcode & 0xf000) == 0xb000) {
+ switch ((opcode >> 8) & 0x0f) {
+ case 0x0:
+ return evaluate_adjust_stack_thumb(opcode, address, instruction);
+ case 0x1:
+ case 0x3:
+ case 0x9:
+ case 0xb:
+ return evaluate_cb_thumb(opcode, address, instruction);
+ case 0x2:
+ return evaluate_extend_thumb(opcode, address, instruction);
+ case 0x4:
+ case 0x5:
+ case 0xc:
+ case 0xd:
+ return evaluate_load_store_multiple_thumb(opcode, address,
+ instruction);
+ case 0x6:
+ return evaluate_cps_thumb(opcode, address, instruction);
+ case 0xa:
+ if ((opcode & 0x00c0) == 0x0080)
+ break;
+ return evaluate_byterev_thumb(opcode, address, instruction);
+ case 0xe:
+ return evaluate_breakpoint_thumb(opcode, address, instruction);
+ case 0xf:
+ if (opcode & 0x000f)
+ return evaluate_ifthen_thumb(opcode, address,
+ instruction);
+ else
+ return evaluate_hint_thumb(opcode, address,
+ instruction);
+ }
+
+ instruction->type = ARM_UNDEFINED_INSTRUCTION;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
+ address, opcode);
+ return ERROR_OK;
+ }
+
+ /* Load/Store multiple */
+ if ((opcode & 0xf000) == 0xc000)
+ return evaluate_load_store_multiple_thumb(opcode, address, instruction);
+
+ /* Conditional branch + SWI */
+ if ((opcode & 0xf000) == 0xd000)
+ return evaluate_cond_branch_thumb(opcode, address, instruction);
+
+ if ((opcode & 0xe000) == 0xe000) {
+ /* Undefined instructions */
+ if ((opcode & 0xf801) == 0xe801) {
+ instruction->type = ARM_UNDEFINED_INSTRUCTION;
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%8.8x\t"
+ "UNDEFINED INSTRUCTION",
+ address, opcode);
+ return ERROR_OK;
+ } else /* Branch to offset */
+ return evaluate_b_bl_blx_thumb(opcode, address, instruction);
+ }
+
+ LOG_ERROR("Thumb: should never reach this point (opcode=%04x)", opcode);