Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / aarch64.c
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index d25c7d30e1c444f98449eea04aee25c0bfc7d659..2e4d0b5c034f4c9d7f4249da109165e1d2aaa033 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -93,6 +93,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
                case ARM_MODE_HYP:
                case ARM_MODE_UND:
                case ARM_MODE_SYS:
+               case ARM_MODE_MON:
                        instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
                        break;
 
@@ -105,7 +106,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
                if (target_mode != ARM_MODE_ANY)
                        armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-               retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg);
+               retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
                if (retval != ERROR_OK)
                        return retval;
 
@@ -172,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
        case ARM_MODE_HYP:
        case ARM_MODE_UND:
        case ARM_MODE_SYS:
+       case ARM_MODE_MON:
                instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
                break;
 
@@ -182,7 +184,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-       retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr,
+       retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
                                aarch64->system_control_reg_curr);
 
        if (target_mode != ARM_MODE_ANY)
@@ -1043,6 +1045,7 @@ static int aarch64_post_debug_entry(struct target *target)
        case ARM_MODE_HYP:
        case ARM_MODE_UND:
        case ARM_MODE_SYS:
+       case ARM_MODE_MON:
                instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
                break;
 
@@ -1055,14 +1058,14 @@ static int aarch64_post_debug_entry(struct target *target)
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-       retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg);
+       retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
        if (retval != ERROR_OK)
                return retval;
 
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
 
-       LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
+       LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
        aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
        if (armv8->armv8_mmu.armv8_cache.info == -1) {
@@ -2047,6 +2050,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
        struct arm *arm = &armv8->arm;
        int retval;
 
+       if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
+               LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state");
+               return ERROR_FAIL;
+       }
+
        armv8_reg_current(arm, 1)->dirty = true;
 
        /* change DCC to normal mode if necessary */
@@ -2059,22 +2067,32 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
        }
 
        while (count) {
-               uint32_t data, opcode;
+               uint32_t opcode;
+               uint64_t data;
 
-               /* write the data to store into DTRRX */
+               /* write the data to store into DTRRX (and DTRTX for 64-bit) */
                if (size == 1)
                        data = *buffer;
                else if (size == 2)
                        data = target_buffer_get_u16(target, buffer);
-               else
+               else if (size == 4)
                        data = target_buffer_get_u32(target, buffer);
+               else
+                       data = target_buffer_get_u64(target, buffer);
+
                retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                               armv8->debug_base + CPUV8_DBG_DTRRX, data);
+                               armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data);
+               if (retval == ERROR_OK && size > 4)
+                       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                                       armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32));
                if (retval != ERROR_OK)
                        return retval;
 
                if (arm->core_state == ARM_STATE_AARCH64)
-                       retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
+                       if (size <= 4)
+                               retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
+                       else
+                               retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1));
                else
                        retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
                if (retval != ERROR_OK)
@@ -2084,8 +2102,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
                else if (size == 2)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
-               else
+               else if (size == 4)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
+               else
+                       opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP);
+
                retval = dpm->instr_execute(dpm, opcode);
                if (retval != ERROR_OK)
                        return retval;
@@ -2226,6 +2247,11 @@ static int aarch64_read_cpu_memory_slow(struct target *target,
        struct arm *arm = &armv8->arm;
        int retval;
 
+       if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
+               LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state");
+               return ERROR_FAIL;
+       }
+
        armv8_reg_current(arm, 1)->dirty = true;
 
        /* change DCC to normal mode (if necessary) */
@@ -2238,36 +2264,56 @@ static int aarch64_read_cpu_memory_slow(struct target *target,
        }
 
        while (count) {
-               uint32_t opcode, data;
+               uint32_t opcode;
+               uint32_t lower;
+               uint32_t higher;
+               uint64_t data;
 
                if (size == 1)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
                else if (size == 2)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
-               else
+               else if (size == 4)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
+               else
+                       opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP);
+
                retval = dpm->instr_execute(dpm, opcode);
                if (retval != ERROR_OK)
                        return retval;
 
                if (arm->core_state == ARM_STATE_AARCH64)
-                       retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
+                       if (size <= 4)
+                               retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
+                       else
+                               retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1));
                else
                        retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
                if (retval != ERROR_OK)
                        return retval;
 
                retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                               armv8->debug_base + CPUV8_DBG_DTRTX, &data);
+                               armv8->debug_base + CPUV8_DBG_DTRTX, &lower);
+               if (retval == ERROR_OK) {
+                       if (size > 4)
+                               retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                                               armv8->debug_base + CPUV8_DBG_DTRRX, &higher);
+                       else
+                               higher = 0;
+               }
                if (retval != ERROR_OK)
                        return retval;
 
+               data = (uint64_t)lower | (uint64_t)higher << 32;
+
                if (size == 1)
                        *buffer = (uint8_t)data;
                else if (size == 2)
                        target_buffer_set_u16(target, buffer, (uint16_t)data);
+               else if (size == 4)
+                       target_buffer_set_u32(target, buffer, (uint32_t)data);
                else
-                       target_buffer_set_u32(target, buffer, data);
+                       target_buffer_set_u64(target, buffer, data);
 
                /* Advance */
                buffer += size;
@@ -2848,13 +2894,8 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
         * options, JIM_OK if it correctly parsed the topmost option
         * and JIM_ERR if an error occurred during parameter evaluation.
         * For JIM_CONTINUE, we check our own params.
-        *
-        * adiv5_jim_configure() assumes 'private_config' to point to
-        * 'struct adiv5_private_config'. Override 'private_config'!
         */
-       target->private_config = &pc->adiv5_config;
-       e = adiv5_jim_configure(target, goi);
-       target->private_config = pc;
+       e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
        if (e != JIM_CONTINUE)
                return e;
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)