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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / aarch64.c
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 6c9673fa23b98981e9631c43dd7b20ce5f3acbff..2e4d0b5c034f4c9d7f4249da109165e1d2aaa033 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -21,6 +21,7 @@
 #include "arm_semihosting.h"
 #include "jtag/interface.h"
 #include "smp.h"
+#include <helper/nvp.h>
 #include <helper/time_support.h>
 
 enum restart_mode {
@@ -92,6 +93,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
                case ARM_MODE_HYP:
                case ARM_MODE_UND:
                case ARM_MODE_SYS:
+               case ARM_MODE_MON:
                        instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
                        break;
 
@@ -104,7 +106,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
                if (target_mode != ARM_MODE_ANY)
                        armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-               retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg);
+               retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
                if (retval != ERROR_OK)
                        return retval;
 
@@ -171,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
        case ARM_MODE_HYP:
        case ARM_MODE_UND:
        case ARM_MODE_SYS:
+       case ARM_MODE_MON:
                instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
                break;
 
@@ -181,7 +184,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-       retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr,
+       retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
                                aarch64->system_control_reg_curr);
 
        if (target_mode != ARM_MODE_ANY)
@@ -588,7 +591,7 @@ static int aarch64_restore_one(struct target *target, int current,
                        resume_pc &= 0xFFFFFFFC;
                        break;
                case ARM_STATE_AARCH64:
-                       resume_pc &= 0xFFFFFFFFFFFFFFFC;
+                       resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
                        break;
                case ARM_STATE_THUMB:
                case ARM_STATE_THUMB_EE:
@@ -845,8 +848,10 @@ static int aarch64_resume(struct target *target, int current,
        struct armv8_common *armv8 = target_to_armv8(target);
        armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME;
 
-       if (target->state != TARGET_HALTED)
+       if (target->state != TARGET_HALTED) {
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
+       }
 
        /*
         * If this target is part of a SMP group, prepare the others
@@ -1040,6 +1045,7 @@ static int aarch64_post_debug_entry(struct target *target)
        case ARM_MODE_HYP:
        case ARM_MODE_UND:
        case ARM_MODE_SYS:
+       case ARM_MODE_MON:
                instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
                break;
 
@@ -1052,14 +1058,14 @@ static int aarch64_post_debug_entry(struct target *target)
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, target_mode);
 
-       retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg);
+       retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
        if (retval != ERROR_OK)
                return retval;
 
        if (target_mode != ARM_MODE_ANY)
                armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
 
-       LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
+       LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
        aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
        if (armv8->armv8_mmu.armv8_cache.info == -1) {
@@ -1088,13 +1094,14 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
        struct armv8_common *armv8 = target_to_armv8(target);
        struct aarch64_common *aarch64 = target_to_aarch64(target);
        int saved_retval = ERROR_OK;
+       int poll_retval;
        int retval;
        uint32_t edecr;
 
        armv8->last_run_control_op = ARMV8_RUNCONTROL_STEP;
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -1170,6 +1177,8 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
        if (retval == ERROR_TARGET_TIMEOUT)
                saved_retval = aarch64_halt_one(target, HALT_SYNC);
 
+       poll_retval = aarch64_poll(target);
+
        /* restore EDECR */
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_EDECR, edecr);
@@ -1186,6 +1195,9 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
        if (saved_retval != ERROR_OK)
                return saved_retval;
 
+       if (poll_retval != ERROR_OK)
+               return poll_retval;
+
        return ERROR_OK;
 }
 
@@ -1248,7 +1260,7 @@ static int aarch64_set_breakpoint(struct target *target,
                        | (byte_addr_select << 5)
                        | (3 << 1) | 1;
                brp_list[brp_i].used = 1;
-               brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
+               brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
                brp_list[brp_i].control = control;
                bpt_value = brp_list[brp_i].value;
 
@@ -1300,28 +1312,28 @@ static int aarch64_set_breakpoint(struct target *target,
                buf_set_u32(code, 0, 32, opcode);
 
                retval = target_read_memory(target,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length, 1,
                                breakpoint->orig_instr);
                if (retval != ERROR_OK)
                        return retval;
 
                armv8_cache_d_inner_flush_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
 
                retval = target_write_memory(target,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length, 1, code);
                if (retval != ERROR_OK)
                        return retval;
 
                armv8_cache_d_inner_flush_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
 
                armv8_cache_i_inner_inval_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
 
                breakpoint->is_set = true;
@@ -1453,7 +1465,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin
                | (iva_byte_addr_select << 5)
                | (3 << 1) | 1;
        brp_list[brp_2].used = 1;
-       brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
+       brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
        brp_list[brp_2].control = control_iva;
        retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
                        + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
@@ -1577,29 +1589,29 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                /* restore original instruction (kept in target endianness) */
 
                armv8_cache_d_inner_flush_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
 
                if (breakpoint->length == 4) {
                        retval = target_write_memory(target,
-                                       breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                                       breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                        4, 1, breakpoint->orig_instr);
                        if (retval != ERROR_OK)
                                return retval;
                } else {
                        retval = target_write_memory(target,
-                                       breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                                       breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                        2, 1, breakpoint->orig_instr);
                        if (retval != ERROR_OK)
                                return retval;
                }
 
                armv8_cache_d_inner_flush_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
 
                armv8_cache_i_inner_inval_virt(armv8,
-                               breakpoint->address & 0xFFFFFFFFFFFFFFFE,
+                               breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
                                breakpoint->length);
        }
        breakpoint->is_set = false;
@@ -2038,6 +2050,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
        struct arm *arm = &armv8->arm;
        int retval;
 
+       if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
+               LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state");
+               return ERROR_FAIL;
+       }
+
        armv8_reg_current(arm, 1)->dirty = true;
 
        /* change DCC to normal mode if necessary */
@@ -2050,22 +2067,32 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
        }
 
        while (count) {
-               uint32_t data, opcode;
+               uint32_t opcode;
+               uint64_t data;
 
-               /* write the data to store into DTRRX */
+               /* write the data to store into DTRRX (and DTRTX for 64-bit) */
                if (size == 1)
                        data = *buffer;
                else if (size == 2)
                        data = target_buffer_get_u16(target, buffer);
-               else
+               else if (size == 4)
                        data = target_buffer_get_u32(target, buffer);
+               else
+                       data = target_buffer_get_u64(target, buffer);
+
                retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                               armv8->debug_base + CPUV8_DBG_DTRRX, data);
+                               armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data);
+               if (retval == ERROR_OK && size > 4)
+                       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                                       armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32));
                if (retval != ERROR_OK)
                        return retval;
 
                if (arm->core_state == ARM_STATE_AARCH64)
-                       retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
+                       if (size <= 4)
+                               retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
+                       else
+                               retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1));
                else
                        retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
                if (retval != ERROR_OK)
@@ -2075,8 +2102,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target,
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
                else if (size == 2)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
-               else
+               else if (size == 4)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
+               else
+                       opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP);
+
                retval = dpm->instr_execute(dpm, opcode);
                if (retval != ERROR_OK)
                        return retval;
@@ -2134,7 +2164,7 @@ static int aarch64_write_cpu_memory(struct target *target,
        uint32_t dscr;
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -2217,6 +2247,11 @@ static int aarch64_read_cpu_memory_slow(struct target *target,
        struct arm *arm = &armv8->arm;
        int retval;
 
+       if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
+               LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state");
+               return ERROR_FAIL;
+       }
+
        armv8_reg_current(arm, 1)->dirty = true;
 
        /* change DCC to normal mode (if necessary) */
@@ -2229,36 +2264,56 @@ static int aarch64_read_cpu_memory_slow(struct target *target,
        }
 
        while (count) {
-               uint32_t opcode, data;
+               uint32_t opcode;
+               uint32_t lower;
+               uint32_t higher;
+               uint64_t data;
 
                if (size == 1)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
                else if (size == 2)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
-               else
+               else if (size == 4)
                        opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
+               else
+                       opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP);
+
                retval = dpm->instr_execute(dpm, opcode);
                if (retval != ERROR_OK)
                        return retval;
 
                if (arm->core_state == ARM_STATE_AARCH64)
-                       retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
+                       if (size <= 4)
+                               retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
+                       else
+                               retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1));
                else
                        retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
                if (retval != ERROR_OK)
                        return retval;
 
                retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                               armv8->debug_base + CPUV8_DBG_DTRTX, &data);
+                               armv8->debug_base + CPUV8_DBG_DTRTX, &lower);
+               if (retval == ERROR_OK) {
+                       if (size > 4)
+                               retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                                               armv8->debug_base + CPUV8_DBG_DTRRX, &higher);
+                       else
+                               higher = 0;
+               }
                if (retval != ERROR_OK)
                        return retval;
 
+               data = (uint64_t)lower | (uint64_t)higher << 32;
+
                if (size == 1)
                        *buffer = (uint8_t)data;
                else if (size == 2)
                        target_buffer_set_u16(target, buffer, (uint16_t)data);
+               else if (size == 4)
+                       target_buffer_set_u32(target, buffer, (uint32_t)data);
                else
-                       target_buffer_set_u32(target, buffer, data);
+                       target_buffer_set_u64(target, buffer, data);
 
                /* Advance */
                buffer += size;
@@ -2352,7 +2407,7 @@ static int aarch64_read_cpu_memory(struct target *target,
                        address, size, count);
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -2692,6 +2747,9 @@ static int aarch64_examine(struct target *target)
        if (retval == ERROR_OK)
                retval = aarch64_init_debug_access(target);
 
+       if (retval == ERROR_OK)
+               retval = aarch64_poll(target);
+
        return retval;
 }
 
@@ -2789,8 +2847,8 @@ static int aarch64_mmu(struct target *target, int *enabled)
        struct aarch64_common *aarch64 = target_to_aarch64(target);
        struct armv8_common *armv8 = &aarch64->armv8_common;
        if (target->state != TARGET_HALTED) {
-               LOG_ERROR("%s: target %s not halted", __func__, target_name(target));
-               return ERROR_TARGET_INVALID;
+               LOG_TARGET_ERROR(target, "not halted");
+               return ERROR_TARGET_NOT_HALTED;
        }
        if (armv8->is_armv8r)
                *enabled = 0;
@@ -2836,13 +2894,8 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
         * options, JIM_OK if it correctly parsed the topmost option
         * and JIM_ERR if an error occurred during parameter evaluation.
         * For JIM_CONTINUE, we check our own params.
-        *
-        * adiv5_jim_configure() assumes 'private_config' to point to
-        * 'struct adiv5_private_config'. Override 'private_config'!
         */
-       target->private_config = &pc->adiv5_config;
-       e = adiv5_jim_configure(target, goi);
-       target->private_config = pc;
+       e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
        if (e != JIM_CONTINUE)
                return e;
 
@@ -2957,15 +3010,15 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command)
        struct target *target = get_current_target(CMD_CTX);
        struct aarch64_common *aarch64 = target_to_aarch64(target);
 
-       static const struct jim_nvp nvp_maskisr_modes[] = {
+       static const struct nvp nvp_maskisr_modes[] = {
                { .name = "off", .value = AARCH64_ISRMASK_OFF },
                { .name = "on", .value = AARCH64_ISRMASK_ON },
                { .name = NULL, .value = -1 },
        };
-       const struct jim_nvp *n;
+       const struct nvp *n;
 
        if (CMD_ARGC > 0) {
-               n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
+               n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]);
                if (!n->name) {
                        LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
                        return ERROR_COMMAND_SYNTAX_ERROR;
@@ -2974,7 +3027,7 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command)
                aarch64->isrmasking_mode = n->value;
        }
 
-       n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
+       n = nvp_value2name(nvp_maskisr_modes, aarch64->isrmasking_mode);
        command_print(CMD, "aarch64 interrupt mask %s", n->name);
 
        return ERROR_OK;
@@ -3009,8 +3062,10 @@ COMMAND_HANDLER(aarch64_mcrmrc_command)
                return ERROR_FAIL;
        }
 
-       if (target->state != TARGET_HALTED)
+       if (target->state != TARGET_HALTED) {
+               command_print(CMD, "Error: [%s] not halted", target_name(target));
                return ERROR_TARGET_NOT_HALTED;
+       }
 
        if (arm->core_state == ARM_STATE_AARCH64) {
                command_print(CMD, "%s: not 32-bit arm target", target_name(target));
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