-/* SPDX-License-Identifier: GPL-2.0-or-later */
+// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
if (!stm32x_info->otp_unlocked) {
- LOG_INFO("OTP memory bank #%u is is enabled for write commands.",
+ LOG_INFO("OTP memory bank #%u is enabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = true;
} else {
- LOG_WARNING("OTP memory bank #%u is is already enabled for write commands.",
+ LOG_WARNING("OTP memory bank #%u is already enabled for write commands.",
bank->bank_number);
}
return ERROR_OK;
}
if (stm32x_is_otp(bank)) {
- if (!set)
+ if (!set) {
+ LOG_ERROR("OTP protection can only be enabled");
return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
return stm32x_otp_protect(bank, first, last);
}
return retval;
if ((*device_id & 0xfff) == 0x411
- && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) {
+ && cortex_m_get_impl_part(target) == CORTEX_M4_PARTNO) {
*device_id &= ~((0xFFFF << 16) | 0xfff);
*device_id |= (0x1000 << 16) | 0x413;
LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
COMMAND_HANDLER(stm32x_handle_mass_erase_command)
{
- if (CMD_ARGC < 1) {
- command_print(CMD, "stm32x mass_erase <bank>");
+ if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
struct flash_bank *bank;
struct stm32x_flash_bank *stm32x_info = NULL;
- if (CMD_ARGC != 1) {
- command_print(CMD, "stm32f2x options_read <bank>");
+ if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (retval != ERROR_OK)
struct stm32x_flash_bank *stm32x_info = NULL;
uint16_t user_options, boot_addr0, boot_addr1, options_mask;
- if (CMD_ARGC < 1) {
- command_print(CMD, "stm32f2x options_write <bank> ...");
+ if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (retval != ERROR_OK)
stm32x_info = bank->driver_priv;
if (stm32x_info->has_boot_addr) {
- if (CMD_ARGC != 4) {
- command_print(CMD, "stm32f2x options_write <bank> <user_options>"
- " <boot_addr0> <boot_addr1>");
+ if (CMD_ARGC != 4)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
+
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
- } else {
- if (CMD_ARGC != 2) {
- command_print(CMD, "stm32f2x options_write <bank> <user_options>");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
+ } else if (CMD_ARGC != 2) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
struct stm32x_flash_bank *stm32x_info = NULL;
uint32_t optcr2_pcrop;
- if (CMD_ARGC != 2) {
- command_print(CMD, "stm32f2x optcr2_write <bank> <optcr2_value>");
+ if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (retval != ERROR_OK)
COMMAND_HANDLER(stm32x_handle_otp_command)
{
- if (CMD_ARGC < 2) {
- command_print(CMD, "stm32x otp <bank> (enable|disable|show)");
+ if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
.name = "otp",
.handler = stm32x_handle_otp_command,
.mode = COMMAND_EXEC,
- .usage = "bank_id",
+ .usage = "bank_id (enable|disable|show)",
.help = "OTP (One Time Programmable) memory write enable/disable.",
},
COMMAND_REGISTRATION_DONE