1 # script for stm32f7x family
4 # stm32f7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f7x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 128kB
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x20000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0385
31 # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
32 set _CPUTAPID 0x5ba00477
34 set _CPUTAPID 0x5ba02477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
42 jtag newtap $_CHIPNAME bs -irlen 5
45 set _TARGETNAME $_CHIPNAME.cpu
46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
50 set _FLASHNAME $_CHIPNAME.flash
51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
53 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
56 adapter_nsrst_delay 100
61 # use hardware reset, connect under reset
62 reset_config srst_only srst_nogate
65 # if srst is not fitted use SYSRESETREQ to
66 # perform a soft reset
67 cortex_m reset_config sysresetreq
70 $_TARGETNAME configure -event examine-end {
71 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
72 mmw 0xE0042004 0x00000007 0
74 # Stop watchdog counters during halt
75 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
76 mmw 0xE0042008 0x00001800 0
79 $_TARGETNAME configure -event trace-config {
80 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
81 # change this value accordingly to configure trace pins
83 mmw 0xE0042004 0x00000020 0
86 $_TARGETNAME configure -event reset-init {
87 # Configure PLL to boost clock to HSI x 10 (160 MHz)
88 mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
89 mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
90 mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
91 sleep 10 ;# Wait for PLL to lock
92 mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
93 mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
96 # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
97 # suffers from DAP WAITs
99 [[target current] cget -dap] memaccess 16
105 $_TARGETNAME configure -event reset-start {
106 # Reduce speed since CPU speed will slow down to 16MHz with the reset
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