1 # script for stm32f3x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f3x
17 # Work-area is a space in RAM used for flash programming
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x4000
25 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
27 # Since we may be running of an RC oscilator, we crank down the speed a
28 # bit more to be on the safe side. Perhaps superstition, but if are
29 # running off a crystal, we can run closer to the limit. Note
30 # that there can be a pretty wide band where things are more or less stable.
33 adapter_nsrst_delay 100
39 if { [info exists CPUTAPID] } {
40 set _CPUTAPID $CPUTAPID
43 # See STM Document RM0316
44 # Section 29.6.3 - corresponds to Cortex-M4 r0p1
45 set _CPUTAPID 0x4ba00477
47 set _CPUTAPID 0x2ba01477
51 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
52 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
55 jtag newtap $_CHIPNAME bs -irlen 5
58 set _TARGETNAME $_CHIPNAME.cpu
59 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
61 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
63 set _FLASHNAME $_CHIPNAME.flash
64 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
66 reset_config srst_nogate
69 # if srst is not fitted use SYSRESETREQ to
70 # perform a soft reset
71 cortex_m reset_config sysresetreq
74 proc stm32f3x_default_reset_start {} {
75 # Reset clock is HSI (8 MHz)
79 proc stm32f3x_default_examine_end {} {
80 # Enable debug during low power modes (uses more power)
81 mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
83 # Stop watchdog counters during halt
84 mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
87 proc stm32f3x_default_reset_init {} {
88 # Configure PLL to boost clock to HSI x 8 (64 MHz)
89 mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
90 mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
91 mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
92 sleep 10 ;# Wait for PLL to lock
93 mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
95 # Boost JTAG frequency
100 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
101 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
102 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
104 $_TARGETNAME configure -event trace-config {
105 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
106 # change this value accordingly to configure trace pins
108 mmw 0xe0042004 0x00000020 0
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