7 ######################################
8 # Target: Atmel AT91SAM9260
9 ######################################
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME at91sam9260
17 if { [info exists ENDIAN] } {
23 if { [info exists CPUTAPID ] } {
24 set _CPUTAPID $CPUTAPID
26 # force an error till we get a good number
27 set _CPUTAPID 0x0792603f
30 reset_config trst_and_srst
33 adapter_nsrst_delay 200
37 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
40 ######################
41 # Target configuration
42 ######################
44 set _TARGETNAME $_CHIPNAME.cpu
45 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
47 $_TARGETNAME invoke-event halted
49 # Internal sram1 memory
50 $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
53 $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
57 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
58 set _FLASHNAME $_CHIPNAME.flash
59 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
62 proc at91sam_init { } {
64 # at reset chip runs at 32khz
67 mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
68 mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
70 mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
72 mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
74 mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
76 mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
78 mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
81 # Now run at anything fast... ie: 10mhz!
82 adapter_khz 10000 # Increase JTAG Speed to 6 MHz
83 arm7_9 dcc_downloads enable # Enable faster DCC downloads
85 mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
86 mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
87 mww 0xffffec08 0x00160016 # SMC_CYCLE0
88 mww 0xffffec0c 0x00161003 # SMC_MODE0
90 flash probe 0 # Identify flash bank 0
92 mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
93 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
95 mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
97 mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
98 #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
100 mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
102 mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
104 mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
120 mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
122 mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
124 mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)