1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
32 #include "breakpoints.h"
35 #include "mips32_dmaacc.h"
36 #include "target_type.h"
39 static void mips_m4k_enable_breakpoints(struct target
*target
);
40 static void mips_m4k_enable_watchpoints(struct target
*target
);
41 static int mips_m4k_set_breakpoint(struct target
*target
,
42 struct breakpoint
*breakpoint
);
43 static int mips_m4k_unset_breakpoint(struct target
*target
,
44 struct breakpoint
*breakpoint
);
45 static int mips_m4k_internal_restore(struct target
*target
, int current
,
46 uint32_t address
, int handle_breakpoints
,
48 static int mips_m4k_halt(struct target
*target
);
49 static int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
50 uint32_t count
, const uint8_t *buffer
);
52 static int mips_m4k_examine_debug_reason(struct target
*target
)
54 struct mips32_common
*mips32
= target_to_mips32(target
);
55 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
56 uint32_t break_status
;
59 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
60 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
61 if (ejtag_info
->debug_caps
& EJTAG_DCR_IB
) {
62 /* get info about inst breakpoint support */
63 retval
= target_read_u32(target
,
64 ejtag_info
->ejtag_ibs_addr
, &break_status
);
65 if (retval
!= ERROR_OK
)
67 if (break_status
& 0x1f) {
68 /* we have halted on a breakpoint */
69 retval
= target_write_u32(target
,
70 ejtag_info
->ejtag_ibs_addr
, 0);
71 if (retval
!= ERROR_OK
)
73 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
77 if (ejtag_info
->debug_caps
& EJTAG_DCR_DB
) {
78 /* get info about data breakpoint support */
79 retval
= target_read_u32(target
,
80 ejtag_info
->ejtag_dbs_addr
, &break_status
);
81 if (retval
!= ERROR_OK
)
83 if (break_status
& 0x1f) {
84 /* we have halted on a breakpoint */
85 retval
= target_write_u32(target
,
86 ejtag_info
->ejtag_dbs_addr
, 0);
87 if (retval
!= ERROR_OK
)
89 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
97 static int mips_m4k_debug_entry(struct target
*target
)
99 struct mips32_common
*mips32
= target_to_mips32(target
);
100 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
102 mips32_save_context(target
);
104 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
105 mips_ejtag_config_step(ejtag_info
, 0);
107 /* make sure break unit configured */
108 mips32_configure_break_unit(target
);
110 /* attempt to find halt reason */
111 mips_m4k_examine_debug_reason(target
);
113 /* default to mips32 isa, it will be changed below if required */
114 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
116 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
117 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
119 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
120 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
121 target_state_name(target
));
126 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
128 struct target_list
*head
;
132 while (head
!= (struct target_list
*)NULL
) {
134 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
141 static int mips_m4k_halt_smp(struct target
*target
)
143 int retval
= ERROR_OK
;
144 struct target_list
*head
;
147 while (head
!= (struct target_list
*)NULL
) {
150 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
151 ret
= mips_m4k_halt(curr
);
153 if (ret
!= ERROR_OK
) {
154 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
162 static int update_halt_gdb(struct target
*target
)
164 int retval
= ERROR_OK
;
165 if (target
->gdb_service
->core
[0] == -1) {
166 target
->gdb_service
->target
= target
;
167 target
->gdb_service
->core
[0] = target
->coreid
;
168 retval
= mips_m4k_halt_smp(target
);
173 static int mips_m4k_poll(struct target
*target
)
175 int retval
= ERROR_OK
;
176 struct mips32_common
*mips32
= target_to_mips32(target
);
177 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
178 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
179 enum target_state prev_target_state
= target
->state
;
181 /* toggle to another core is done by gdb as follow */
182 /* maint packet J core_id */
184 /* the next polling trigger an halt event sent to gdb */
185 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
186 (target
->gdb_service
) &&
187 (target
->gdb_service
->target
== NULL
)) {
188 target
->gdb_service
->target
=
189 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
190 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
194 /* read ejtag control reg */
195 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
196 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
197 if (retval
!= ERROR_OK
)
200 /* clear this bit before handling polling
201 * as after reset registers will read zero */
202 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
203 /* we have detected a reset, clear flag
204 * otherwise ejtag will not work */
205 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
207 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
208 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
209 if (retval
!= ERROR_OK
)
211 LOG_DEBUG("Reset Detected");
214 /* check for processor halted */
215 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
216 if ((target
->state
!= TARGET_HALTED
)
217 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
218 if (target
->state
== TARGET_UNKNOWN
)
219 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
221 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
222 * (maybe put on by HALT-ing the board in the previous session).
224 * Force enable debug entry for this session.
226 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
227 target
->state
= TARGET_HALTED
;
228 retval
= mips_m4k_debug_entry(target
);
229 if (retval
!= ERROR_OK
)
233 ((prev_target_state
== TARGET_RUNNING
)
234 || (prev_target_state
== TARGET_RESET
))) {
235 retval
= update_halt_gdb(target
);
236 if (retval
!= ERROR_OK
)
239 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
240 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
241 target
->state
= TARGET_HALTED
;
243 retval
= mips_m4k_debug_entry(target
);
244 if (retval
!= ERROR_OK
)
248 retval
= update_halt_gdb(target
);
249 if (retval
!= ERROR_OK
)
253 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
256 target
->state
= TARGET_RUNNING
;
258 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
263 static int mips_m4k_halt(struct target
*target
)
265 struct mips32_common
*mips32
= target_to_mips32(target
);
266 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
268 LOG_DEBUG("target->state: %s", target_state_name(target
));
270 if (target
->state
== TARGET_HALTED
) {
271 LOG_DEBUG("target was already halted");
275 if (target
->state
== TARGET_UNKNOWN
)
276 LOG_WARNING("target was in unknown state when halt was requested");
278 if (target
->state
== TARGET_RESET
) {
279 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
280 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
281 return ERROR_TARGET_FAILURE
;
283 /* we came here in a reset_halt or reset_init sequence
284 * debug entry was already prepared in mips_m4k_assert_reset()
286 target
->debug_reason
= DBG_REASON_DBGRQ
;
292 /* break processor */
293 mips_ejtag_enter_debug(ejtag_info
);
295 target
->debug_reason
= DBG_REASON_DBGRQ
;
300 static int mips_m4k_assert_reset(struct target
*target
)
302 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
303 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
305 /* TODO: apply hw reset signal in not examined state */
306 if (!(target_was_examined(target
))) {
307 LOG_WARNING("Reset is not asserted because the target is not examined.");
308 LOG_WARNING("Use a reset button or power cycle the target.");
309 return ERROR_TARGET_NOT_EXAMINED
;
312 LOG_DEBUG("target->state: %s",
313 target_state_name(target
));
315 enum reset_types jtag_reset_config
= jtag_get_reset_config();
317 /* some cores support connecting while srst is asserted
318 * use that mode is it has been configured */
320 bool srst_asserted
= false;
322 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
323 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
324 jtag_add_reset(0, 1);
325 srst_asserted
= true;
329 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
330 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
) {
331 if (target
->reset_halt
) {
332 /* use hardware to catch reset */
333 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
335 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
338 if (jtag_reset_config
& RESET_HAS_SRST
) {
339 /* here we should issue a srst only, but we may have to assert trst as well */
340 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
341 jtag_add_reset(1, 1);
342 else if (!srst_asserted
)
343 jtag_add_reset(0, 1);
345 if (mips_m4k
->is_pic32mx
) {
346 LOG_DEBUG("Using MTAP reset to reset processor...");
348 /* use microchip specific MTAP reset */
349 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
350 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
352 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
353 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
354 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
356 /* use ejtag reset - not supported by all cores */
357 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
358 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
359 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
360 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
364 target
->state
= TARGET_RESET
;
365 jtag_add_sleep(50000);
367 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
369 if (target
->reset_halt
) {
370 int retval
= target_halt(target
);
371 if (retval
!= ERROR_OK
)
378 static int mips_m4k_deassert_reset(struct target
*target
)
380 LOG_DEBUG("target->state: %s", target_state_name(target
));
382 /* deassert reset lines */
383 jtag_add_reset(0, 0);
388 static int mips_m4k_single_step_core(struct target
*target
)
390 struct mips32_common
*mips32
= target_to_mips32(target
);
391 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
393 /* configure single step mode */
394 mips_ejtag_config_step(ejtag_info
, 1);
396 /* disable interrupts while stepping */
397 mips32_enable_interrupts(target
, 0);
399 /* exit debug mode */
400 mips_ejtag_exit_debug(ejtag_info
);
402 mips_m4k_debug_entry(target
);
407 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
409 int retval
= ERROR_OK
;
410 struct target_list
*head
;
414 while (head
!= (struct target_list
*)NULL
) {
417 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
418 /* resume current address , not in step mode */
419 ret
= mips_m4k_internal_restore(curr
, 1, address
,
420 handle_breakpoints
, 0);
422 if (ret
!= ERROR_OK
) {
423 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
424 curr
->coreid
, address
);
433 static int mips_m4k_internal_restore(struct target
*target
, int current
,
434 uint32_t address
, int handle_breakpoints
, int debug_execution
)
436 struct mips32_common
*mips32
= target_to_mips32(target
);
437 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
438 struct breakpoint
*breakpoint
= NULL
;
441 if (target
->state
!= TARGET_HALTED
) {
442 LOG_WARNING("target not halted");
443 return ERROR_TARGET_NOT_HALTED
;
446 if (!debug_execution
) {
447 target_free_all_working_areas(target
);
448 mips_m4k_enable_breakpoints(target
);
449 mips_m4k_enable_watchpoints(target
);
452 /* current = 1: continue on current pc, otherwise continue at <address> */
454 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
455 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
456 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
459 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
460 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
465 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
467 mips32_restore_context(target
);
469 /* the front-end may request us not to handle breakpoints */
470 if (handle_breakpoints
) {
471 /* Single step past breakpoint at current address */
472 breakpoint
= breakpoint_find(target
, resume_pc
);
474 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
475 mips_m4k_unset_breakpoint(target
, breakpoint
);
476 mips_m4k_single_step_core(target
);
477 mips_m4k_set_breakpoint(target
, breakpoint
);
481 /* enable interrupts if we are running */
482 mips32_enable_interrupts(target
, !debug_execution
);
484 /* exit debug mode */
485 mips_ejtag_exit_debug(ejtag_info
);
486 target
->debug_reason
= DBG_REASON_NOTHALTED
;
488 /* registers are now invalid */
489 register_cache_invalidate(mips32
->core_cache
);
491 if (!debug_execution
) {
492 target
->state
= TARGET_RUNNING
;
493 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
494 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
496 target
->state
= TARGET_DEBUG_RUNNING
;
497 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
498 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
504 static int mips_m4k_resume(struct target
*target
, int current
,
505 uint32_t address
, int handle_breakpoints
, int debug_execution
)
507 int retval
= ERROR_OK
;
509 /* dummy resume for smp toggle in order to reduce gdb impact */
510 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
511 /* simulate a start and halt of target */
512 target
->gdb_service
->target
= NULL
;
513 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
514 /* fake resume at next poll we play the target core[1], see poll*/
515 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
519 retval
= mips_m4k_internal_restore(target
, current
, address
,
523 if (retval
== ERROR_OK
&& target
->smp
) {
524 target
->gdb_service
->core
[0] = -1;
525 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
531 static int mips_m4k_step(struct target
*target
, int current
,
532 uint32_t address
, int handle_breakpoints
)
534 /* get pointers to arch-specific information */
535 struct mips32_common
*mips32
= target_to_mips32(target
);
536 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
537 struct breakpoint
*breakpoint
= NULL
;
539 if (target
->state
!= TARGET_HALTED
) {
540 LOG_WARNING("target not halted");
541 return ERROR_TARGET_NOT_HALTED
;
544 /* current = 1: continue on current pc, otherwise continue at <address> */
546 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
547 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
548 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
551 /* the front-end may request us not to handle breakpoints */
552 if (handle_breakpoints
) {
553 breakpoint
= breakpoint_find(target
,
554 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
556 mips_m4k_unset_breakpoint(target
, breakpoint
);
559 /* restore context */
560 mips32_restore_context(target
);
562 /* configure single step mode */
563 mips_ejtag_config_step(ejtag_info
, 1);
565 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
567 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
569 /* disable interrupts while stepping */
570 mips32_enable_interrupts(target
, 0);
572 /* exit debug mode */
573 mips_ejtag_exit_debug(ejtag_info
);
575 /* registers are now invalid */
576 register_cache_invalidate(mips32
->core_cache
);
578 LOG_DEBUG("target stepped ");
579 mips_m4k_debug_entry(target
);
582 mips_m4k_set_breakpoint(target
, breakpoint
);
584 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
589 static void mips_m4k_enable_breakpoints(struct target
*target
)
591 struct breakpoint
*breakpoint
= target
->breakpoints
;
593 /* set any pending breakpoints */
595 if (breakpoint
->set
== 0)
596 mips_m4k_set_breakpoint(target
, breakpoint
);
597 breakpoint
= breakpoint
->next
;
601 static int mips_m4k_set_breakpoint(struct target
*target
,
602 struct breakpoint
*breakpoint
)
604 struct mips32_common
*mips32
= target_to_mips32(target
);
605 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
606 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
609 if (breakpoint
->set
) {
610 LOG_WARNING("breakpoint already set");
614 if (breakpoint
->type
== BKPT_HARD
) {
617 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
619 if (bp_num
>= mips32
->num_inst_bpoints
) {
620 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
621 breakpoint
->unique_id
);
622 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
624 breakpoint
->set
= bp_num
+ 1;
625 comparator_list
[bp_num
].used
= 1;
626 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
628 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
629 * Warning: there is no IB ASID registers in 2.0.
630 * Do not set it! :) */
631 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
632 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
634 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
635 comparator_list
[bp_num
].bp_value
);
636 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
637 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
638 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
639 ejtag_info
->ejtag_ibc_offs
, 1);
640 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
641 breakpoint
->unique_id
,
642 bp_num
, comparator_list
[bp_num
].bp_value
);
643 } else if (breakpoint
->type
== BKPT_SOFT
) {
644 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
645 if (breakpoint
->length
== 4) {
646 uint32_t verify
= 0xffffffff;
648 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
649 breakpoint
->orig_instr
);
650 if (retval
!= ERROR_OK
)
652 retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
);
653 if (retval
!= ERROR_OK
)
656 retval
= target_read_u32(target
, breakpoint
->address
, &verify
);
657 if (retval
!= ERROR_OK
)
659 if (verify
!= MIPS32_SDBBP
) {
660 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
661 " - check that memory is read/writable", breakpoint
->address
);
665 uint16_t verify
= 0xffff;
667 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
668 breakpoint
->orig_instr
);
669 if (retval
!= ERROR_OK
)
671 retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
);
672 if (retval
!= ERROR_OK
)
675 retval
= target_read_u16(target
, breakpoint
->address
, &verify
);
676 if (retval
!= ERROR_OK
)
678 if (verify
!= MIPS16_SDBBP
) {
679 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
680 " - check that memory is read/writable", breakpoint
->address
);
685 breakpoint
->set
= 20; /* Any nice value but 0 */
691 static int mips_m4k_unset_breakpoint(struct target
*target
,
692 struct breakpoint
*breakpoint
)
694 /* get pointers to arch-specific information */
695 struct mips32_common
*mips32
= target_to_mips32(target
);
696 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
697 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
700 if (!breakpoint
->set
) {
701 LOG_WARNING("breakpoint not set");
705 if (breakpoint
->type
== BKPT_HARD
) {
706 int bp_num
= breakpoint
->set
- 1;
707 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
)) {
708 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
709 breakpoint
->unique_id
);
712 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
713 breakpoint
->unique_id
,
715 comparator_list
[bp_num
].used
= 0;
716 comparator_list
[bp_num
].bp_value
= 0;
717 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
718 ejtag_info
->ejtag_ibc_offs
, 0);
721 /* restore original instruction (kept in target endianness) */
722 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
723 if (breakpoint
->length
== 4) {
724 uint32_t current_instr
;
726 /* check that user program has not modified breakpoint instruction */
727 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
728 (uint8_t *)¤t_instr
);
729 if (retval
!= ERROR_OK
)
733 * target_read_memory() gets us data in _target_ endianess.
734 * If we want to use this data on the host for comparisons with some macros
735 * we must first transform it to _host_ endianess using target_buffer_get_u32().
737 current_instr
= target_buffer_get_u32(target
, (uint8_t *)¤t_instr
);
739 if (current_instr
== MIPS32_SDBBP
) {
740 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
741 breakpoint
->orig_instr
);
742 if (retval
!= ERROR_OK
)
746 uint16_t current_instr
;
748 /* check that user program has not modified breakpoint instruction */
749 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
750 (uint8_t *)¤t_instr
);
751 if (retval
!= ERROR_OK
)
753 current_instr
= target_buffer_get_u16(target
, (uint8_t *)¤t_instr
);
754 if (current_instr
== MIPS16_SDBBP
) {
755 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
756 breakpoint
->orig_instr
);
757 if (retval
!= ERROR_OK
)
767 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
769 struct mips32_common
*mips32
= target_to_mips32(target
);
771 if (breakpoint
->type
== BKPT_HARD
) {
772 if (mips32
->num_inst_bpoints_avail
< 1) {
773 LOG_INFO("no hardware breakpoint available");
774 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
777 mips32
->num_inst_bpoints_avail
--;
780 return mips_m4k_set_breakpoint(target
, breakpoint
);
783 static int mips_m4k_remove_breakpoint(struct target
*target
,
784 struct breakpoint
*breakpoint
)
786 /* get pointers to arch-specific information */
787 struct mips32_common
*mips32
= target_to_mips32(target
);
789 if (target
->state
!= TARGET_HALTED
) {
790 LOG_WARNING("target not halted");
791 return ERROR_TARGET_NOT_HALTED
;
795 mips_m4k_unset_breakpoint(target
, breakpoint
);
797 if (breakpoint
->type
== BKPT_HARD
)
798 mips32
->num_inst_bpoints_avail
++;
803 static int mips_m4k_set_watchpoint(struct target
*target
,
804 struct watchpoint
*watchpoint
)
806 struct mips32_common
*mips32
= target_to_mips32(target
);
807 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
808 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
811 * watchpoint enabled, ignore all byte lanes in value register
812 * and exclude both load and store accesses from watchpoint
813 * condition evaluation
815 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
816 (0xff << EJTAG_DBCn_BLM_SHIFT
);
818 if (watchpoint
->set
) {
819 LOG_WARNING("watchpoint already set");
823 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
825 if (wp_num
>= mips32
->num_data_bpoints
) {
826 LOG_ERROR("Can not find free FP Comparator");
830 if (watchpoint
->length
!= 4) {
831 LOG_ERROR("Only watchpoints of length 4 are supported");
832 return ERROR_TARGET_UNALIGNED_ACCESS
;
835 if (watchpoint
->address
% 4) {
836 LOG_ERROR("Watchpoints address should be word aligned");
837 return ERROR_TARGET_UNALIGNED_ACCESS
;
840 switch (watchpoint
->rw
) {
842 enable
&= ~EJTAG_DBCn_NOLB
;
845 enable
&= ~EJTAG_DBCn_NOSB
;
848 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
851 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
854 watchpoint
->set
= wp_num
+ 1;
855 comparator_list
[wp_num
].used
= 1;
856 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
858 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
859 * There is as well no ASID register support. */
860 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
861 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
863 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
864 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
866 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
867 comparator_list
[wp_num
].bp_value
);
868 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
869 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
871 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
872 ejtag_info
->ejtag_dbc_offs
, enable
);
873 /* TODO: probably this value is ignored on 2.0 */
874 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
875 ejtag_info
->ejtag_dbv_offs
, 0);
876 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
881 static int mips_m4k_unset_watchpoint(struct target
*target
,
882 struct watchpoint
*watchpoint
)
884 /* get pointers to arch-specific information */
885 struct mips32_common
*mips32
= target_to_mips32(target
);
886 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
887 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
889 if (!watchpoint
->set
) {
890 LOG_WARNING("watchpoint not set");
894 int wp_num
= watchpoint
->set
- 1;
895 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
)) {
896 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
899 comparator_list
[wp_num
].used
= 0;
900 comparator_list
[wp_num
].bp_value
= 0;
901 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
902 ejtag_info
->ejtag_dbc_offs
, 0);
908 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
910 struct mips32_common
*mips32
= target_to_mips32(target
);
912 if (mips32
->num_data_bpoints_avail
< 1) {
913 LOG_INFO("no hardware watchpoints available");
914 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
917 mips32
->num_data_bpoints_avail
--;
919 mips_m4k_set_watchpoint(target
, watchpoint
);
923 static int mips_m4k_remove_watchpoint(struct target
*target
,
924 struct watchpoint
*watchpoint
)
926 /* get pointers to arch-specific information */
927 struct mips32_common
*mips32
= target_to_mips32(target
);
929 if (target
->state
!= TARGET_HALTED
) {
930 LOG_WARNING("target not halted");
931 return ERROR_TARGET_NOT_HALTED
;
935 mips_m4k_unset_watchpoint(target
, watchpoint
);
937 mips32
->num_data_bpoints_avail
++;
942 static void mips_m4k_enable_watchpoints(struct target
*target
)
944 struct watchpoint
*watchpoint
= target
->watchpoints
;
946 /* set any pending watchpoints */
948 if (watchpoint
->set
== 0)
949 mips_m4k_set_watchpoint(target
, watchpoint
);
950 watchpoint
= watchpoint
->next
;
954 static int mips_m4k_read_memory(struct target
*target
, uint32_t address
,
955 uint32_t size
, uint32_t count
, uint8_t *buffer
)
957 struct mips32_common
*mips32
= target_to_mips32(target
);
958 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
960 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
961 address
, size
, count
);
963 if (target
->state
!= TARGET_HALTED
) {
964 LOG_WARNING("target not halted");
965 return ERROR_TARGET_NOT_HALTED
;
968 /* sanitize arguments */
969 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
970 return ERROR_COMMAND_SYNTAX_ERROR
;
972 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
973 return ERROR_TARGET_UNALIGNED_ACCESS
;
975 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
979 t
= malloc(count
* size
* sizeof(uint8_t));
981 LOG_ERROR("Out of memory");
987 /* if noDMA off, use DMAACC mode for memory read */
989 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
990 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
992 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
994 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
995 /* endianness, but byte array should represent target endianness */
996 if (ERROR_OK
== retval
) {
999 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1002 target_buffer_set_u16_array(target
, buffer
, count
, t
);
1007 if ((size
> 1) && (t
!= NULL
))
1013 static int mips_m4k_write_memory(struct target
*target
, uint32_t address
,
1014 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1016 struct mips32_common
*mips32
= target_to_mips32(target
);
1017 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1019 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1020 address
, size
, count
);
1022 if (target
->state
!= TARGET_HALTED
) {
1023 LOG_WARNING("target not halted");
1024 return ERROR_TARGET_NOT_HALTED
;
1027 if (size
== 4 && count
> 32) {
1028 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1029 if (retval
== ERROR_OK
)
1031 LOG_WARNING("Falling back to non-bulk write");
1034 /* sanitize arguments */
1035 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1036 return ERROR_COMMAND_SYNTAX_ERROR
;
1038 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1039 return ERROR_TARGET_UNALIGNED_ACCESS
;
1041 /** correct endianess if we have word or hword access */
1044 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1045 /* endianness, but byte array represents target endianness */
1046 t
= malloc(count
* size
* sizeof(uint8_t));
1048 LOG_ERROR("Out of memory");
1054 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1057 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1063 /* if noDMA off, use DMAACC mode for memory write */
1065 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1066 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1068 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1073 if (ERROR_OK
!= retval
)
1079 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1080 struct target
*target
)
1082 mips32_build_reg_cache(target
);
1087 static int mips_m4k_init_arch_info(struct target
*target
,
1088 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1090 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1092 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1094 /* initialize mips4k specific info */
1095 mips32_init_arch_info(target
, mips32
, tap
);
1096 mips32
->arch_info
= mips_m4k
;
1101 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1103 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1105 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1110 static int mips_m4k_examine(struct target
*target
)
1113 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1114 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1115 uint32_t idcode
= 0;
1117 if (!target_was_examined(target
)) {
1118 retval
= mips_ejtag_get_idcode(ejtag_info
, &idcode
);
1119 if (retval
!= ERROR_OK
)
1121 ejtag_info
->idcode
= idcode
;
1123 if (((idcode
>> 1) & 0x7FF) == 0x29) {
1124 /* we are using a pic32mx so select ejtag port
1125 * as it is not selected by default */
1126 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1127 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1128 mips_m4k
->is_pic32mx
= true;
1132 /* init rest of ejtag interface */
1133 retval
= mips_ejtag_init(ejtag_info
);
1134 if (retval
!= ERROR_OK
)
1137 retval
= mips32_examine(target
);
1138 if (retval
!= ERROR_OK
)
1144 static int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
1145 uint32_t count
, const uint8_t *buffer
)
1147 struct mips32_common
*mips32
= target_to_mips32(target
);
1148 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1149 struct working_area
*fast_data_area
;
1153 LOG_DEBUG("address: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, count
);
1155 /* check alignment */
1157 return ERROR_TARGET_UNALIGNED_ACCESS
;
1159 if (mips32
->fast_data_area
== NULL
) {
1160 /* Get memory for block write handler
1161 * we preserve this area between calls and gain a speed increase
1162 * of about 3kb/sec when writing flash
1163 * this will be released/nulled by the system when the target is resumed or reset */
1164 retval
= target_alloc_working_area(target
,
1165 MIPS32_FASTDATA_HANDLER_SIZE
,
1166 &mips32
->fast_data_area
);
1167 if (retval
!= ERROR_OK
) {
1168 LOG_ERROR("No working area available");
1172 /* reset fastadata state so the algo get reloaded */
1173 ejtag_info
->fast_access_save
= -1;
1176 fast_data_area
= mips32
->fast_data_area
;
1178 if (address
<= fast_data_area
->address
+ fast_data_area
->size
&&
1179 fast_data_area
->address
<= address
+ count
) {
1180 LOG_ERROR("fast_data (0x%8.8" PRIx32
") is within write area "
1181 "(0x%8.8" PRIx32
"-0x%8.8" PRIx32
").",
1182 fast_data_area
->address
, address
, address
+ count
);
1183 LOG_ERROR("Change work-area-phys or load_image address!");
1187 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1188 /* but byte array represents target endianness */
1190 t
= malloc(count
* sizeof(uint32_t));
1192 LOG_ERROR("Out of memory");
1196 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1198 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1204 if (retval
!= ERROR_OK
)
1205 LOG_ERROR("Fastdata access Failed");
1210 static int mips_m4k_verify_pointer(struct command_context
*cmd_ctx
,
1211 struct mips_m4k_common
*mips_m4k
)
1213 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1214 command_print(cmd_ctx
, "target is not an MIPS_M4K");
1215 return ERROR_TARGET_INVALID
;
1220 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1223 struct target
*target
= get_current_target(CMD_CTX
);
1224 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1225 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1227 retval
= mips_m4k_verify_pointer(CMD_CTX
, mips_m4k
);
1228 if (retval
!= ERROR_OK
)
1231 if (target
->state
!= TARGET_HALTED
) {
1232 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1236 /* two or more argument, access a single register/select (write if third argument is given) */
1238 return ERROR_COMMAND_SYNTAX_ERROR
;
1240 uint32_t cp0_reg
, cp0_sel
;
1241 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1242 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1244 if (CMD_ARGC
== 2) {
1246 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1247 if (retval
!= ERROR_OK
) {
1248 command_print(CMD_CTX
,
1249 "couldn't access reg %" PRIi32
,
1253 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1254 cp0_reg
, cp0_sel
, value
);
1256 } else if (CMD_ARGC
== 3) {
1258 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1259 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1260 if (retval
!= ERROR_OK
) {
1261 command_print(CMD_CTX
,
1262 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
1266 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1267 cp0_reg
, cp0_sel
, value
);
1274 COMMAND_HANDLER(mips_m4k_handle_smp_off_command
)
1276 struct target
*target
= get_current_target(CMD_CTX
);
1277 /* check target is an smp target */
1278 struct target_list
*head
;
1279 struct target
*curr
;
1280 head
= target
->head
;
1282 if (head
!= (struct target_list
*)NULL
) {
1283 while (head
!= (struct target_list
*)NULL
) {
1284 curr
= head
->target
;
1288 /* fixes the target display to the debugger */
1289 target
->gdb_service
->target
= target
;
1294 COMMAND_HANDLER(mips_m4k_handle_smp_on_command
)
1296 struct target
*target
= get_current_target(CMD_CTX
);
1297 struct target_list
*head
;
1298 struct target
*curr
;
1299 head
= target
->head
;
1300 if (head
!= (struct target_list
*)NULL
) {
1302 while (head
!= (struct target_list
*)NULL
) {
1303 curr
= head
->target
;
1311 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command
)
1313 struct target
*target
= get_current_target(CMD_CTX
);
1314 int retval
= ERROR_OK
;
1315 struct target_list
*head
;
1316 head
= target
->head
;
1317 if (head
!= (struct target_list
*)NULL
) {
1318 if (CMD_ARGC
== 1) {
1320 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
1321 if (ERROR_OK
!= retval
)
1323 target
->gdb_service
->core
[1] = coreid
;
1326 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
1327 , target
->gdb_service
->core
[1]);
1332 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1334 struct target
*target
= get_current_target(CMD_CTX
);
1335 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1336 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1339 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1340 else if (CMD_ARGC
> 1)
1341 return ERROR_COMMAND_SYNTAX_ERROR
;
1343 command_print(CMD_CTX
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1344 if (ejtag_info
->scan_delay
>= 2000000) {
1345 ejtag_info
->mode
= 0;
1346 command_print(CMD_CTX
, "running in legacy mode");
1348 ejtag_info
->mode
= 1;
1349 command_print(CMD_CTX
, "running in fast queued mode");
1355 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1358 .handler
= mips_m4k_handle_cp0_command
,
1359 .mode
= COMMAND_EXEC
,
1360 .usage
= "regnum [value]",
1361 .help
= "display/modify cp0 register",
1365 .handler
= mips_m4k_handle_smp_off_command
,
1366 .mode
= COMMAND_EXEC
,
1367 .help
= "Stop smp handling",
1372 .handler
= mips_m4k_handle_smp_on_command
,
1373 .mode
= COMMAND_EXEC
,
1374 .help
= "Restart smp handling",
1379 .handler
= mips_m4k_handle_smp_gdb_command
,
1380 .mode
= COMMAND_EXEC
,
1381 .help
= "display/fix current core played to gdb",
1385 .name
= "scan_delay",
1386 .handler
= mips_m4k_handle_scan_delay_command
,
1387 .mode
= COMMAND_ANY
,
1388 .help
= "display/set scan delay in nano seconds",
1391 COMMAND_REGISTRATION_DONE
1394 const struct command_registration mips_m4k_command_handlers
[] = {
1396 .chain
= mips32_command_handlers
,
1400 .mode
= COMMAND_ANY
,
1401 .help
= "mips_m4k command group",
1403 .chain
= mips_m4k_exec_command_handlers
,
1405 COMMAND_REGISTRATION_DONE
1408 struct target_type mips_m4k_target
= {
1411 .poll
= mips_m4k_poll
,
1412 .arch_state
= mips32_arch_state
,
1414 .halt
= mips_m4k_halt
,
1415 .resume
= mips_m4k_resume
,
1416 .step
= mips_m4k_step
,
1418 .assert_reset
= mips_m4k_assert_reset
,
1419 .deassert_reset
= mips_m4k_deassert_reset
,
1421 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1423 .read_memory
= mips_m4k_read_memory
,
1424 .write_memory
= mips_m4k_write_memory
,
1425 .checksum_memory
= mips32_checksum_memory
,
1426 .blank_check_memory
= mips32_blank_check_memory
,
1428 .run_algorithm
= mips32_run_algorithm
,
1430 .add_breakpoint
= mips_m4k_add_breakpoint
,
1431 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1432 .add_watchpoint
= mips_m4k_add_watchpoint
,
1433 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1435 .commands
= mips_m4k_command_handlers
,
1436 .target_create
= mips_m4k_target_create
,
1437 .init_target
= mips_m4k_init_target
,
1438 .examine
= mips_m4k_examine
,
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