3 source [find interface/sheevaplug.cfg]
4 source [find target/feroceon.cfg]
6 $_TARGETNAME configure -event reset-init { sheevaplug_init }
8 $_TARGETNAME configure \
9 -work-area-phys 0x10000000 \
10 -work-area-size 65536 \
13 arm7_9 dcc_downloads enable
15 # this assumes the hardware default peripherals location before u-Boot moves it
16 nand device orion 0 0xd8000000
18 proc sheevaplug_init { } {
20 arm926ejs cp15 0 0 1 0 0x00052078
22 mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
23 mww 0xD0001404 0x39543000 # Dunit Control Low Register
24 mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
25 mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
26 mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
27 mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
28 mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
29 mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
30 mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
31 mww 0xD0001424 0x0000F17F # Dunit Control High Register
32 mww 0xD0001428 0x00085520 # Dunit Control High Register
33 mww 0xD000147c 0x00008552 # Dunit Control High Register
34 mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
35 mww 0xD0001508 0x10000000 # CS1n Base Register
36 mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
37 mww 0xD0001514 0x00000000 # CS2n Size Register
38 mww 0xD000151C 0x00000000 # CS3n Size Register
39 mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
40 mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
41 mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
42 mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
43 mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
44 mww 0xD0020204 0x00000000 # "
45 mww 0xD0020204 0x00000000 # "
46 mww 0xD0020204 0x00000000 # "
47 mww 0xD0020204 0x00000000 # "
48 mww 0xD0020204 0x00000000 # "
49 mww 0xD0020204 0x00000000 # "
50 mww 0xD0020204 0x00000000 # "
51 mww 0xD0020204 0x00000000 # "
52 mww 0xD0020204 0x00000000 # "
53 mww 0xD0020204 0x00000000 # "
54 mww 0xD0020204 0x00000000 # "
55 mww 0xD0020204 0x00000000 # "
56 mww 0xD0020204 0x00000000 # "
57 mww 0xD0020204 0x00000000 # "
58 mww 0xD0020204 0x00000000 # "
59 mww 0xD0020204 0x00000000 # "
60 mww 0xD0020204 0x00000000 # "
61 mww 0xD0020204 0x00000000 # "
62 mww 0xD0020204 0x00000000 # "
63 mww 0xD0020204 0x00000000 # "
64 mww 0xD0020204 0x00000000 # "
65 mww 0xD0020204 0x00000000 # "
66 mww 0xD0020204 0x00000000 # "
67 mww 0xD0020204 0x00000000 # "
68 mww 0xD0020204 0x00000000 # "
69 mww 0xD0020204 0x00000000 # "
70 mww 0xD0020204 0x00000000 # "
71 mww 0xD0020204 0x00000000 # "
72 mww 0xD0020204 0x00000000 # "
73 mww 0xD0020204 0x00000000 # "
74 mww 0xD0020204 0x00000000 # "
75 mww 0xD0020204 0x00000000 # "
76 mww 0xD0020204 0x00000000 # "
77 mww 0xD0020204 0x00000000 # "
78 mww 0xD0020204 0x00000000 # "
79 mww 0xD0020204 0x00000000 # "
81 mww 0xD0010000 0x01111111 # MPP 0 to 7
82 mww 0xD0010004 0x11113322 # MPP 8 to 15
83 mww 0xD0010008 0x00001111 # MPP 16 to 23
85 mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
86 mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
87 mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
91 proc sheevaplug_reflash_uboot { } {
93 # reflash the u-Boot binary
97 nand write 0 uboot.bin 0
102 proc sheevaplug_load_uboot { } {
104 # load u-Boot into RAM
106 load_image /tmp/uboot.elf
107 verify_image uboot.elf