Nicolas Pitre nico at cam.org SheevaPlug board configuration

git-svn-id: svn://svn.berlios.de/openocd/trunk@1391 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/board/sheevaplug.cfg b/src/target/board/sheevaplug.cfg
new file mode 100644 (file)
index 0000000..2dd2cae
--- /dev/null
+++ b/src/target/board/sheevaplug.cfg
@@ -0,0 +1,111 @@
+# Marvell SheevaPlug \r
+\r
+source [find interface/sheevaplug.cfg]\r
+source [find target/feroceon.cfg]\r
+\r
+$_TARGETNAME configure -event reset-init { sheevaplug_init }\r
+\r
+$_TARGETNAME configure \\r
+       -work-area-phys 0x10000000 \\r
+       -work-area-size 65536 \\r
+       -work-area-backup 0\r
+\r
+arm7_9 dcc_downloads enable\r
+\r
+# this assumes the hardware default peripherals location before u-Boot moves it\r
+nand device orion 0 0xd8000000\r
+\r
+proc sheevaplug_init { } {\r
+\r
+       arm926ejs cp15 0 0 1 0 0x00052078\r
+\r
+       mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register\r
+       mww 0xD0001404 0x39543000 #  Dunit Control Low Register\r
+       mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register\r
+       mww 0xD000140C 0x00000833 #  DDR SDRAM Timing (High) Register\r
+       mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register\r
+       mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register\r
+       mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register\r
+       mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register\r
+       mww 0xD0001420 0x00000042 #  DDR SDRAM Extended Mode Register\r
+       mww 0xD0001424 0x0000F17F #  Dunit Control High Register\r
+       mww 0xD0001428 0x00085520 #  Dunit Control High Register\r
+       mww 0xD000147c 0x00008552 #  Dunit Control High Register\r
+       mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register\r
+       mww 0xD0001508 0x10000000 #  CS1n Base Register\r
+       mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register\r
+       mww 0xD0001514 0x00000000 #  CS2n Size Register\r
+       mww 0xD000151C 0x00000000 #  CS3n Size Register\r
+       mww 0xD0001494 0x003C0000 #  DDR2 SDRAM ODT Control (Low) Register\r
+       mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister\r
+       mww 0xD000149C 0x0000F80F #  DDR2 Dunit ODT Control Register\r
+       mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register\r
+       mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+       mww 0xD0020204 0x00000000 #              "\r
+\r
+       mww 0xD0010000 0x01111111 #  MPP  0 to 7\r
+       mww 0xD0010004 0x11113322 #  MPP  8 to 15\r
+       mww 0xD0010008 0x00001111 #  MPP 16 to 23\r
+\r
+       mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister\r
+       mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register\r
+       mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register\r
+\r
+}\r
+\r
+proc sheevaplug_reflash_uboot { } {\r
+\r
+       # reflash the u-Boot binary\r
+       #reset init\r
+       nand probe 0\r
+       nand erase 0 0 4\r
+       nand write 0 uboot.bin 0\r
+       reset run\r
+\r
+}\r
+\r
+proc sheevaplug_load_uboot { } {\r
+\r
+       # load u-Boot into RAM\r
+       #reset init\r
+       load_image /tmp/uboot.elf\r
+       verify_image uboot.elf\r
+       resume 0x00600000\r
+\r
+}\r
+\r