src/target/armv7a.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *    Copyright (C) 2009 by David Brownell                                 *
   5  ***************************************************************************/
   6
   7 #ifndef OPENOCD_TARGET_ARMV7A_H
   8 #define OPENOCD_TARGET_ARMV7A_H
   9
  10 #include "arm_adi_v5.h"
  11 #include "armv7a_cache.h"
  12 #include "arm.h"
  13 #include "armv4_5_mmu.h"
  14 #include "armv4_5_cache.h"
  15 #include "arm_dpm.h"
  16
  17 enum {
  18         ARM_PC  = 15,
  19         ARM_CPSR = 16
  20 };
  21
  22 #define ARMV7_COMMON_MAGIC 0x0A450999
  23
  24 /* VA to PA translation operations opc2 values*/
  25 #define V2PCWPR  0
  26 #define V2PCWPW  1
  27 #define V2PCWUR  2
  28 #define V2PCWUW  3
  29 #define V2POWPR  4
  30 #define V2POWPW  5
  31 #define V2POWUR  6
  32 #define V2POWUW  7
  33 /*   L210/L220 cache controller support */
  34 struct armv7a_l2x_cache {
  35         uint32_t base;
  36         uint32_t way;
  37 };
  38
  39 struct armv7a_cachesize {
  40         /*  cache dimensioning */
  41         uint32_t linelen;
  42         uint32_t associativity;
  43         uint32_t nsets;
  44         uint32_t cachesize;
  45         /* info for set way operation on cache */
  46         uint32_t index;
  47         uint32_t index_shift;
  48         uint32_t way;
  49         uint32_t way_shift;
  50 };
  51
  52 /* information about one architecture cache at any level */
  53 struct armv7a_arch_cache {
  54         int ctype;                              /* cache type, CLIDR encoding */
  55         struct armv7a_cachesize d_u_size;       /* data cache */
  56         struct armv7a_cachesize i_size;         /* instruction cache */
  57 };
  58
  59 /* common cache information */
  60 struct armv7a_cache_common {
  61         int info;                               /* -1 invalid, else valid */
  62         int loc;                                /* level of coherency */
  63         uint32_t dminline;                      /* minimum d-cache linelen */
  64         uint32_t iminline;                      /* minimum i-cache linelen */
  65         struct armv7a_arch_cache arch[6];       /* cache info, L1 - L7 */
  66         int i_cache_enabled;
  67         int d_u_cache_enabled;
  68         int auto_cache_enabled;                 /* openocd automatic
  69                                                  * cache handling */
  70         /* outer unified cache if some */
  71         void *outer_cache;
  72         int (*flush_all_data_cache)(struct target *target);
  73 };
  74
  75 struct armv7a_mmu_common {
  76         /* following field mmu working way */
  77         int32_t cached;     /* 0: not initialized, 1: initialized */
  78         uint32_t ttbcr;     /* cache for ttbcr register */
  79         uint32_t ttbr[2];
  80         uint32_t ttbr_mask[2];
  81         uint32_t ttbr_range[2];
  82
  83         int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
  84                         uint32_t count, uint8_t *buffer);
  85         struct armv7a_cache_common armv7a_cache;
  86         uint32_t mmu_enabled;
  87 };
  88
  89 struct armv7a_common {
  90         struct arm arm;
  91         int common_magic;
  92         struct reg_cache *core_cache;
  93
  94         /* Core Debug Unit */
  95         struct arm_dpm dpm;
  96         target_addr_t debug_base;
  97         struct adiv5_ap *debug_ap;
  98         /* mdir */
  99         uint8_t multi_processor_system;
 100         uint8_t multi_threading_processor;
 101         uint8_t level2_id;
 102         uint8_t cluster_id;
 103         uint8_t cpu_id;
 104         bool is_armv7r;
 105         uint32_t rev;
 106         uint32_t partnum;
 107         uint32_t arch;
 108         uint32_t variant;
 109         uint32_t implementor;
 110
 111         /* cache specific to V7 Memory Management Unit compatible with v4_5*/
 112         struct armv7a_mmu_common armv7a_mmu;
 113
 114         int (*examine_debug_reason)(struct target *target);
 115         int (*post_debug_entry)(struct target *target);
 116
 117         void (*pre_restore_context)(struct target *target);
 118 };
 119
 120 static inline struct armv7a_common *
 121 target_to_armv7a(struct target *target)
 122 {
 123         return container_of(target->arch_info, struct armv7a_common, arm);
 124 }
 125
 126 static inline bool is_armv7a(struct armv7a_common *armv7a)
 127 {
 128         return armv7a->common_magic == ARMV7_COMMON_MAGIC;
 129 }
 130
 131
 132 /* register offsets from armv7a.debug_base */
 133
 134 /* See ARMv7a arch spec section C10.2 */
 135 #define CPUDBG_DIDR             0x000
 136
 137 /* See ARMv7a arch spec section C10.3 */
 138 #define CPUDBG_WFAR             0x018
 139 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
 140 #define CPUDBG_DSCR             0x088
 141 #define CPUDBG_DRCR             0x090
 142 #define CPUDBG_PRCR             0x310
 143 #define CPUDBG_PRSR             0x314
 144
 145 /* See ARMv7a arch spec section C10.4 */
 146 #define CPUDBG_DTRRX            0x080
 147 #define CPUDBG_ITR              0x084
 148 #define CPUDBG_DTRTX            0x08c
 149
 150 /* See ARMv7a arch spec section C10.5 */
 151 #define CPUDBG_BVR_BASE         0x100
 152 #define CPUDBG_BCR_BASE         0x140
 153 #define CPUDBG_WVR_BASE         0x180
 154 #define CPUDBG_WCR_BASE         0x1C0
 155 #define CPUDBG_VCR              0x01C
 156
 157 /* See ARMv7a arch spec section C10.6 */
 158 #define CPUDBG_OSLAR            0x300
 159 #define CPUDBG_OSLSR            0x304
 160 #define CPUDBG_OSSRR            0x308
 161 #define CPUDBG_ECR              0x024
 162
 163 /* See ARMv7a arch spec section C10.7 */
 164 #define CPUDBG_DSCCR            0x028
 165 #define CPUDBG_DSMCR            0x02C
 166
 167 /* See ARMv7a arch spec section C10.8 */
 168 #define CPUDBG_AUTHSTATUS       0xFB8
 169
 170 /* See ARMv7a arch spec DDI 0406C C11.10 */
 171 #define CPUDBG_ID_PFR1          0xD24
 172
 173 /* Masks for Vector Catch register */
 174 #define DBG_VCR_FIQ_MASK        ((1 << 31) | (1 << 7))
 175 #define DBG_VCR_IRQ_MASK        ((1 << 30) | (1 << 6))
 176 #define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
 177 #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
 178 #define DBG_VCR_SVC_MASK        ((1 << 26) | (1 << 2))
 179
 180 /* Masks for Multiprocessor Affinity Register */
 181 #define MPIDR_MP_EXT            (1UL << 31)
 182
 183 int armv7a_arch_state(struct target *target);
 184 int armv7a_identify_cache(struct target *target);
 185 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 186
 187 int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 188                 struct armv7a_cache_common *armv7a_cache);
 189 int armv7a_read_ttbcr(struct target *target);
 190
 191 extern const struct command_registration armv7a_command_handlers[];
 192
 193 #endif /* OPENOCD_TARGET_ARMV7A_H */