1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2009 by David Brownell *
5 ***************************************************************************/
7 #ifndef OPENOCD_TARGET_ARMV7A_H
8 #define OPENOCD_TARGET_ARMV7A_H
10 #include "arm_adi_v5.h"
11 #include "armv7a_cache.h"
13 #include "armv4_5_mmu.h"
14 #include "armv4_5_cache.h"
22 #define ARMV7_COMMON_MAGIC 0x0A450999U
24 /* VA to PA translation operations opc2 values*/
33 /* L210/L220 cache controller support */
34 struct armv7a_l2x_cache
{
39 struct armv7a_cachesize
{
40 /* cache dimensioning */
42 uint32_t associativity
;
45 /* info for set way operation on cache */
52 /* information about one architecture cache at any level */
53 struct armv7a_arch_cache
{
54 int ctype
; /* cache type, CLIDR encoding */
55 struct armv7a_cachesize d_u_size
; /* data cache */
56 struct armv7a_cachesize i_size
; /* instruction cache */
59 /* common cache information */
60 struct armv7a_cache_common
{
61 int info
; /* -1 invalid, else valid */
62 int loc
; /* level of coherency */
63 uint32_t dminline
; /* minimum d-cache linelen */
64 uint32_t iminline
; /* minimum i-cache linelen */
65 struct armv7a_arch_cache arch
[6]; /* cache info, L1 - L7 */
67 int d_u_cache_enabled
;
68 int auto_cache_enabled
; /* openocd automatic
70 /* outer unified cache if some */
72 int (*flush_all_data_cache
)(struct target
*target
);
75 struct armv7a_mmu_common
{
76 /* following field mmu working way */
77 int32_t cached
; /* 0: not initialized, 1: initialized */
78 uint32_t ttbcr
; /* cache for ttbcr register */
80 uint32_t ttbr_mask
[2];
81 uint32_t ttbr_range
[2];
83 int (*read_physical_memory
)(struct target
*target
, target_addr_t address
, uint32_t size
,
84 uint32_t count
, uint8_t *buffer
);
85 struct armv7a_cache_common armv7a_cache
;
89 struct armv7a_common
{
90 unsigned int common_magic
;
93 struct reg_cache
*core_cache
;
97 target_addr_t debug_base
;
98 struct adiv5_ap
*debug_ap
;
100 uint8_t multi_processor_system
;
101 uint8_t multi_threading_processor
;
110 uint32_t implementor
;
112 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
113 struct armv7a_mmu_common armv7a_mmu
;
115 int (*examine_debug_reason
)(struct target
*target
);
116 int (*post_debug_entry
)(struct target
*target
);
118 void (*pre_restore_context
)(struct target
*target
);
121 static inline struct armv7a_common
*
122 target_to_armv7a(struct target
*target
)
124 return container_of(target
->arch_info
, struct armv7a_common
, arm
);
127 static inline bool is_armv7a(struct armv7a_common
*armv7a
)
129 return armv7a
->common_magic
== ARMV7_COMMON_MAGIC
;
133 /* register offsets from armv7a.debug_base */
135 /* See ARMv7a arch spec section C10.2 */
136 #define CPUDBG_DIDR 0x000
138 /* See ARMv7a arch spec section C10.3 */
139 #define CPUDBG_WFAR 0x018
140 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
141 #define CPUDBG_DSCR 0x088
142 #define CPUDBG_DRCR 0x090
143 #define CPUDBG_PRCR 0x310
144 #define CPUDBG_PRSR 0x314
146 /* See ARMv7a arch spec section C10.4 */
147 #define CPUDBG_DTRRX 0x080
148 #define CPUDBG_ITR 0x084
149 #define CPUDBG_DTRTX 0x08c
151 /* See ARMv7a arch spec section C10.5 */
152 #define CPUDBG_BVR_BASE 0x100
153 #define CPUDBG_BCR_BASE 0x140
154 #define CPUDBG_WVR_BASE 0x180
155 #define CPUDBG_WCR_BASE 0x1C0
156 #define CPUDBG_VCR 0x01C
158 /* See ARMv7a arch spec section C10.6 */
159 #define CPUDBG_OSLAR 0x300
160 #define CPUDBG_OSLSR 0x304
161 #define CPUDBG_OSSRR 0x308
162 #define CPUDBG_ECR 0x024
164 /* See ARMv7a arch spec section C10.7 */
165 #define CPUDBG_DSCCR 0x028
166 #define CPUDBG_DSMCR 0x02C
168 /* See ARMv7a arch spec section C10.8 */
169 #define CPUDBG_AUTHSTATUS 0xFB8
171 /* See ARMv7a arch spec DDI 0406C C11.10 */
172 #define CPUDBG_ID_PFR1 0xD24
174 /* Masks for Vector Catch register */
175 #define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
176 #define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
177 #define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
178 #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
179 #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
181 /* Masks for Multiprocessor Affinity Register */
182 #define MPIDR_MP_EXT (1UL << 31)
184 int armv7a_arch_state(struct target
*target
);
185 int armv7a_identify_cache(struct target
*target
);
186 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
);
188 int armv7a_handle_cache_info_command(struct command_invocation
*cmd
,
189 struct armv7a_cache_common
*armv7a_cache
);
190 int armv7a_read_ttbcr(struct target
*target
);
192 extern const struct command_registration armv7a_command_handlers
[];
194 #endif /* OPENOCD_TARGET_ARMV7A_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)